參數(shù)資料
型號(hào)： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁(yè)數(shù)： 49/102頁(yè)
文件大小： 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
Two choices of address timing are dynamically se-
lectable: non-pipelined or pipelined. After an idle bus
state, the processor always uses non-pipelined ad-
dress timing. However the NA
Y
(Next Address) in-
put may be asserted to select pipelined address tim-
ing for the next bus cycle. When pipelining is select-
ed and the Intel386 SX Microprocessor has a bus
request pending internally, the address and defini-
tion of the next cycle is made available even before
the current bus cycle is acknowledged by READY
Y
.
Terminating a read or write cycle, like any bus cycle,
requires acknowledging the cycle by asserting the
READY
Y
input. Until acknowledged, the processor
inserts wait states into the bus cycle, to allow adjust-
ment for the speed of any external device. External
hardware, which has decoded the address and bus
cycle type, asserts the READY
Y
input at the appro-
priate time.
At the end of the second bus state within the bus
cycle, READY
Y
is sampled. At that time, if external
hardware acknowledges the bus cycle by asserting
READY
Y
, the bus cycle terminates as shown in Fig-
ure 5.6. If READY
Y
is negated as in Figure 5.7, the
Intel386 SX Microprocessor executes another bus
state (a wait state) and READY
Y
is sampled again
at the end of that state. This continues indefinitely
until the cycle is acknowledged by READY
Y
assert-
ed.
When the current cycle is acknowledged, the
Intel386 SX Microprocessor terminates it. When a
read cycle is acknowledged, the Intel386 SX Micro-
processor latches the information present at its data
pins. When a write cycle is acknowledged, the
Intel386 SX CPU’s write data remains valid through-
out phase one of the next bus state, to provide write
data hold time.
240187–22
Idle states are shown here for diagram variety only. Write cycles are
not
always followed by an idle state. An active bus
cycle can immediately follow the write cycle.
Figure 5.7. Various Bus Cycles with Non-Pipelined Address (various number of wait states)
49
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