參數(shù)資料
型號(hào): KU386
廠商: Intel Corp.
英文描述: SX MICROPROCESSOR
中文描述: SX微處理器
文件頁數(shù): 40/102頁
文件大?。?/td> 1268K
代理商: KU386
Intel386
TM
SX MICROPROCESSOR
CLOCK (CLK2)
CLK2 provides the fundamental timing for the
Intel386 SX Microprocessor. It is divided by two in-
ternally to generate the internal processor clock
used for instruction execution. The internal clock is
comprised of two phases, ‘phase one‘ and ‘phase
two‘. Each CLK2 period is a phase of the internal
clock. Figure 5.2 illustrates the relationship. If de-
sired, the phase of the internal processor clock can
be synchronized to a known phase by ensuring the
falling edge of the RESET signal meets the applica-
ble setup and hold times t
25
and t
26
.
DATA BUS (D
15
–D
0
)
These three-state bidirectional signals provide the
general purpose data path between the Intel386 SX
Microprocessor and other devices. The data bus
outputs are active HIGH and will float during bus
hold acknowledge. Data bus reads require that read-
data setup and hold times t
21
and t
22
be met relative
to CLK2 for correct operation.
240187–16
Figure 5.1. Functional Signal Groups
240187–17
Figure 5.2. CLK2 Signal and Internal Processor Clock
40
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