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參數(shù)資料
| 型號： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 47/102頁 |
| 文件大小： | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
when the Intel386 SX Microprocessor issues a new
bus cycle definition and address.
Collectively, the address bus, data bus and all asso-
ciated control signals are referred to simply as ‘the
bus’. When active, the bus performs one of the bus
cycles below:
1. Read from memory space
2. Locked read from memory space
3. Write to memory space
4. Locked write to memory space
5. Read from I/O space (or coprocessor)
6. Write to I/O space (or coprocessor)
7. Interrupt acknowledge (always locked)
8. Indicate halt, or indicate shutdown
Table 5.2 shows the encoding of the bus cycle defi-
nition signals for each bus cycle. See
Bus Cycle
Definition Signals
for additional information.
When the Intel386 SX Microprocessor bus is not
performing one of the activities listed above, it is ei-
ther Idle or in the Hold Acknowledge state, which
may be detected externally. The idle state can be
identified by the Intel386 SX Microprocessor giving
no further assertions on its address strobe output
(ADS
Y
) since the beginning of its most recent bus
cycle, and the most recent bus cycle having been
terminated. The hold acknowledge state is identified
by the Intel386 SX Microprocessor asserting its hold
acknowledge (HLDA) output.
The shortest time unit of bus activity is a bus state. A
bus state is one processor clock period (two CLK2
periods) in duration. A complete data transfer occurs
during a bus cycle, composed of two or more bus
states.
The fastest Intel386 SX Microprocessor bus cycle
requires only two bus states. For example, three
consecutive bus read cycles, each consisting of two
bus states, are shown by Figure 5.4. The bus states
in each cycle are named T1 and T2. Any memory or
I/O address may be accessed by such a two-state
bus cycle, if the external hardware is fast enough.
240187–20
Fastest pipelined bus cycles consist of T1P and T2P
Figure 5.5. Fastest Read Cycles with Pipelined Address Timing
47
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