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參數(shù)資料
| 型號： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 44/102頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This pin is pro-
vided with a weak internal pull-up resistor of around
20 K-ohms to Vcc so that it will not float active when
left unconnected.
BUSY
Y
serves an additional function. If BUSY
Y
is
sampled LOW at the falling edge of RESET, the
Intel386 SX Microprocessor performs an internal
self-test (see
Bus Activity During and Following
Reset
. If BUSY
Y
is sampled HIGH, no self-test is
performed.
Coprocessor Error (ERROR
Y
)
When asserted (LOW), this input signal indicates
that the previous coprocessor instruction generated
a coprocessor error of a type not masked by the
coprocessor’s control register. This input is automat-
ically sampled by the Intel386 SX Microprocessor
when a coprocessor instruction is encountered, and
if active, the Intel386 SX Microprocessor generates
exception 16 to access the error-handling software.
Several coprocessor instructions, generally those
which clear the numeric error flags in the coproces-
sor or save coprocessor state, do execute without
the Intel386 SX Microprocessor generating excep-
tion 16 even if ERROR
Y
is active. These instruc-
tions are FNINIT, FNCLEX, FNSTSW, FNSTSWAX,
FNSTCW, FNSTENV and FNSAVE.
ERROR
Y
is an active LOW, level-sensitive asyn-
chronous signal. Setup and hold times, t
29
and t
30
,
relative to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This pin is pro-
vided with a weak internal pull-up resistor of around
20 K-ohms to Vcc so that it will not float active when
left unconnected.
INTERRUPT SIGNALS (INTR, NMI, RESET)
The following descriptions cover inputs that can in-
terrupt or suspend execution of the processor’s cur-
rent instruction stream.
Maskable Interrupt Request (INTR)
When asserted, this input indicates a request for in-
terrupt service, which can be masked by the Intel386
SX CPU Flag Register IF bit. When the Intel386 SX
Microprocessor responds to the INTR input, it per-
forms two interrupt acknowledge bus cycles and, at
the end of the second, latches an 8-bit interrupt vec-
tor on D
7
–D
0
to identify the source of the interrupt.
INTR is an active HIGH, level-sensitive asynchro-
nous signal. Setup and hold times, t
27
and t
28
, rela-
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. To assure rec-
ognition of an INTR request, INTR should remain
active until the first interrupt acknowledge bus cycle
begins. INTR is sampled at the beginning of every
instruction in the Intel386 SX Microprocessor’s Exe-
cution Unit. In order to be recognized at a particular
instruction boundary, INTR must be active at least
eight CLK2 clock periods before the beginning of the
instruction. If recognized, the Intel386 SX Microproc-
essor will begin execution of the interrupt.
Non-Maskable Interrupt Request (NMI))
This input indicates a request for interrupt service
which cannot be masked by software. The non-
maskable interrupt request is always processed ac-
cording to the pointer or gate in slot 2 of the interrupt
table. Because of the fixed NMI slot assignment, no
interrupt acknowledge cycles are performed when
processing NMI.
NMI is an active HIGH, rising edge-sensitive asyn-
chronous signal. Setup and hold times, t
27
and t
28
,
relative to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. To assure rec-
ognition of NMI, it must be inactive for at least eight
CLK2 periods, and then be active for at least eight
CLK2 periods before the beginning of the instruction
boundary in the Intel386 SX Microprocessor’s Exe-
cution Unit.
Once NMI processing has begun, no additional
NMI’s are processed until after the next IRET in-
struction, which is typically the end of the NMI serv-
ice routine. If NMI is re-asserted prior to that time,
however, one rising edge on NMI will be remem-
bered for processing after executing the next IRET
instruction.
Interrupt Latency
The time that elapses before an interrupt request is
serviced (interrupt latency) varies according to sev-
eral factors. This delay must be taken into account
by the interrupt source. Any of the following factors
can affect interrupt latency:
1. If interrupts are masked, an INTR request will not
be recognized until interrupts are reenabled.
2. If an NMI is currently being serviced, an incoming
NMI request will not be recognized until the
Intel386 SX Microprocessor encounters the IRET
instruction.
3. An interrupt request is recognized only on an in-
struction boundary of the Intel386 SX Microproc-
essor’s Execution Unit except for the following
cases:
D Repeat string instructions can be interrupted
after each iteration.
44
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