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參數(shù)資料
| 型號： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 12/102頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
240187–4
Figure 2.3. Address Translation
SEGMENT REGISTER USAGE
The main data structure used to organize memory is
the segment. On the Intel386 SX Microprocessor,
segments are variable sized blocks of linear ad-
dresses which have certain attributes associated
with them. There are two main types of segments,
code and data. The segments are of variable size
and can be as small as 1 byte or as large as 4 giga-
bytes (2
32
bits).
In order to provide compact instruction encoding
and increase processor performance, instructions
do not need to explicitly specify which segment reg-
ister is used. The segment register is automatically
chosen according to the rules of Table 2.3 (Segment
Register Selection Rules). In general, data refer-
ences use the selector contained in the DS register,
stack references use the SS register and instruction
fetches use the CS register. The contents of the In-
struction Pointer provide the offset. Special segment
override prefixes allow the explicit use of a given
segment register, and override the implicit rules list-
ed in Table 2.3. The override prefixes also allow the
use of the ES, FS and GS segment registers.
There are no restrictions regarding the overlapping
of the base addresses of any segments. Thus, all 6
segments could have the base address set to zero
and create a system with a four gigabyte linear ad-
dress space. This creates a system where the virtual
address space is the same as the linear address
space. Further details of segmentation are dis-
cussed in chapter 4
PROTECTED MODE ARCHI-
TECTURE
.
2.4 Addressing Modes
The Intel386 SX Microprocessor provides a total of 8
addressing modes for instructions to specify oper-
ands. The addressing modes are optimized to allow
the efficient execution of high level languages such
as C and FORTRAN, and they cover the vast majori-
ty of data references needed by high-level lan-
guages.
REGISTER AND IMMEDIATE MODES
Two of the addressing modes provide for instruc-
tions that operate on register or immediate oper-
ands:
Register Operand Mode:
The operand is located in
one of the 8, 16 or 32-bit general registers.
Immediate Operand Mode:
The operand is includ-
ed in the instruction as part of the opcode.
12
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