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參數(shù)資料
| 型號(hào)： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 55/102頁 |
| 文件大小： | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
Initiating and Maintaining Pipelined Address
Using the state diagram Figure 5.12, observe the
transitions from an idle state, T
i
, to the beginning of
a pipelined bus cycle T1P. From an idle state, T
i
, the
first bus cycle must begin with T1, and is therefore a
non-pipelined bus cycle. The next bus cycle will be
pipelined, however, provided NA
Y
is asserted and
the first bus cycle ends in a T2P state (the address
for the next bus cycle is driven during T2P). The fast-
est path from an idle state to a bus cycle with pipe-
lined address is shown in bold below:
T
i
, T
i
, T
i
, T1 - T2 - T2P, T1P - T2P,
idle
non-pipelined
states
cycle
pipelined
cycle
T1-T2-T2P are the states of the bus cycle that es-
tablish address pipelining for the next bus cycle,
which begins with T1P. The same is true after a bus
hold state, shown below:
T
h
, T
h
, T
h
, T1 - T2 - T2P, T1P - T2P,
hold acknowledge
non-pipelined
states
pipelined
cycle
cycle
The transition to pipelined address is shown func-
tionally by Figure 5.10 Cycle 1. Note that Cycle 1 is
used to transition into pipelined address timing for
the subsequent Cycles 2, 3 and 4, which are pipe-
lined. The NA
Y
input is asserted at the appropriate
time to select address pipelining for Cycles 2, 3 and
4.
Once a bus cycle is in progress and the current ad-
dress has been valid for one entire bus state, the
NA
Y
input is sampled at the end of every phase one
until the bus cycle is acknowledged. Sampling be-
gins in T2 during Cycle 1 in Figure 5.10. Once NA
Y
is sampled active during the current cycle, the
Intel386 SX Microprocessor is free to drive a new
address and bus cycle definition on the bus as early
as the next bus state. In Figure 5.10 Cycle 1 for
example, the next address is driven during state
T2P. Thus Cycle 1 makes the transition to pipelined
address timing, since it begins with T1 but ends with
T2P. Because the address for Cycle 2 is available
before Cycle 2 begins, Cycle 2 is called a pipelined
bus cycle, and it begins with T1P. Cycle 2 begins as
soon as READY
Y
asserted terminates Cycle 1.
Examples of transition bus cycles are Figure 5.10
Cycle 1 and Figure 5.9 Cycle 2. Figure 5.10 shows
transition during the very first cycle after an idle bus
state, which is the fastest possible transition into ad-
dress pipelining. Figure 5.9 Cycle 2 shows a tran-
sition cycle occurring during a burst of bus cycles. In
any case, a transition cycle is the same whenever it
occurs: it consists at least of T1, T2 (NA
Y
is assert-
ed at that time), and T2P (provided the Intel386 SX
Microprocessor has an internal bus request already
pending, which it almost always has). T2P states are
repeated if wait states are added to the cycle.
Note that only three states (T1, T2 and T2P) are
required in a bus cycle performing a
transition
from
non-pipelined address into pipelined address timing,
for example Figure 5.10 Cycle 1. Figure 5.10 Cycles
2, 3 and 4 show that address pipelining can be main-
tained with two-state bus cycles consisting only of
T1P and T2P.
Once a pipelined bus cycle is in progress, pipelined
timing is maintained for the next cycle by asserting
NA
Y
and detecting that the Intel386 SX Microproc-
essor enters T2P during the current bus cycle. The
current bus cycle must end in state T2P for pipelin-
ing to be maintained in the next cycle. T2P is identi-
fied by the assertion of ADS
Y
. Figures 5.9 and 5.10
however, each show pipelining ending after Cycle 4
because Cycle 4 ends in T2I. This indicates the
Intel386 SX Microprocessor didn’t have an internal
bus request prior to the acknowledgement of Cycle
4. If a cycle ends with a T2 or T2I, the next cycle will
not be pipelined.
Realistically, address pipelining is almost always
maintained as long as NA
Y
is sampled asserted.
This is so because in the absence of any other re-
quest, a code prefetch request is always internally
pending until the instruction decoder and code pre-
fetch queue are completely full. Therefore, address
pipelining is maintained for long bursts of bus cycles,
if the bus is available (i.e., HOLD inactive) and NA
Y
is sampled active in each of the bus cycles.
55
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