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參數(shù)資料
| 型號(hào)： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁(yè)數(shù)： | 68/102頁(yè) |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
7.4 A.C. Specifications
The A.C. specifications given in Tables 7.5 through
7.8 consist of output delays, input setup require-
ments and input hold requirements. All A.C. specifi-
cations are relative to the CLK2 rising edge crossing
the 2.0V level.
A.C. spec measurement is defined by Figure 7.1. In-
puts must be driven to the voltage levels indicated
by Figure 7.1 when A.C. specifications are mea-
sured. Output delays are specified with minimum
and maximum limits measured as shown. The mini-
mum delay times are hold times provided to external
circuitry. Input setup and hold times are specified
as minimums, defining the smallest acceptable sam-
pling window. Within the sampling window, a syn-
chronous input signal must be stable for correct op-
eration.
Outputs ADS
Y
, W/R
Y
, D/C
Y
, M/IO
Y
, LOCK
Y
,
BHE
Y
, BLE
Y
, A
23
–A
1
and HLDA only change at
the beginning of phase one. D
15
–D
0
(write cycles)
only change at the beginning of phase two. The
READY
Y
, HOLD, BUSY
Y
, ERROR
Y
, PEREQ,
FLT
Y
and D
15
–D
0
(read cycles) inputs are sampled
at the beginning of phase one. The NA
Y
, INTR and
NMI inputs are sampled at the beginning of phase
two.
240187–35
LEGEND
A D Maximum Output Delay Spec
B D Minimum Output Delay Spec
C D Minimum Input Setup Spec
D D Minimum Input Hold Spec
Figure 7.1. Drive Levels and Measurement Points for A.C. Specifications
68
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