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參數(shù)資料
| 型號： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 79/102頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
Due to the high operating frequency of Intel386 SX
CPU based systems, there is no buffering between
the Intel386 SX emulation processor (on the emula-
tor probe) and the target system. A direct result of
the non-buffered interconnect is that the ICE-
Intel386 SX emulator shares the address and data
busses with the target system.
In order to avoid problems with the shared bus and
maintain signal integrity, the system designer must
adhere to the following guidelines:
1. The bus controller must only enable data trans-
ceivers onto the data bus during valid read cycles
(initiated by assertion of ADS
Y
) of the Intel386
SX CPU, other local devices or other bus mas-
ters.
2. Before another bus master drives the local proc-
essor address bus, the other master must gain
control of the address bus by asserting HOLD
and receiving the HLDA response.
3. The emulation processor receives the RESET
signal 2 or 4 CLK2 cycles later than an Intel386
SX CPU would, and responds to RESET later.
Correct phase of the response is guaranteed.
In order to avoid problems that might arise due to
the shared busses, an Optional use Isolation Board
(OIB) is included with the emulator hardware. The
OIB may be used to provide buffering between the
emulation processor and the target system, but in-
serts a delay of approximately 10 ns in signal path.
In
ICE-386 SX emulator processor module has several
electrical and mechanical characteristics that should
be taken into consideration when designing the
Intel386 SX CPU system.
addition
to
the
above
considerations,
the
Capacitive Loading:
ICE-Intel386 SX adds up to 27
pF to each Intel386 SX CPU signal.
Drive Requirements:
ICE-Intel386 SX adds one
FAST TTL load on the CLK2, control, address, and
data lines. These loads are within the processor
module and are driven by the Intel386 SX CPU emu-
lation processor, which has standard drive and load-
ing capability listed in Tables 7.3 and 7.4.
Power Requirements:
For noise immunity and
CMOS latch-up protection the ICE-Intel386 SX emu-
lator processor module is powered by the user sys-
tem.
The circuitry on the processor module draws up to
1.4A including the maximum Intel386 SX CPU I
CC
from the user Intel386 SX CPU socket.
Intel386 SX CPU Location and Orientation:
The
ICE-Intel386 SX emulator processor module may re-
quire lateral clearance. Figure 7.12 shows the clear-
ance requirements of the iMP adapter. The optional
isolation board (OIB), which provides extra electrical
buffering and has the same lateral clearance re-
quirements as Figure 7.12, adds an additional 0.5
inches to the vertical clearance requirement. This is
illustrated in Figure 7.13.
Optional Isolation Board (OIB) and the CLK2
speed reduction:
Due to the unbuffered probe de-
sign, the ICE-Intel386 SX emulator is susceptible to
errors on the user’s bus. The OIB allows the ICE-
Intel386 SX emulator to function in user systems
with faults (shorted signals, etc.). After electrical ver-
ification the OIB may be removed. When the OIB is
installed, the user system must have a maximum
CLK2 frequency of 20 MHz.
8.0 DIFFERENCES BETWEEN THE
Intel386
TM
SX CPU AND THE
Intel386
TM
DX CPU
The following are the major differences between the
Intel386 SX CPU and the Intel386 DX CPU:
1. The Intel386 SX CPU generates byte selects on
BHE
Y
and BLE
Y
(like the 8086 and 80286) to
distinguish the upper and lower bytes on its 16-bit
data bus. The Intel386 DX CPU uses four byte
selects, BE0
Y
-BE3
Y
, to distinguish between the
different bytes on its 32-bit bus.
2. The Intel386 SX CPU has no bus sizing option.
The Intel386 DX CPU can select between either
a 32-bit bus or a 16-bit bus by use of the BS16
Y
input. The Intel386 SX CPU has a 16-bit bus size.
3. The NA
Y
pin operation in the Intel386 SX CPU is
identical to that of the NA
Y
pin on the Intel386
DX CPU with one exception: the Intel386 DX CPU
NA
Y
pin cannot be activated on 16-bit bus cy-
cles (where BS16
Y
is LOW in the Intel386 DX
CPU case), whereas NA
Y
can be activated on
any Intel386 SX CPU bus cycle.
4. The contents of all Intel386 SX CPU registers at
reset are identical to the contents of the Intel386
DX CPU registers at reset, except the DX regis-
ter. The DX register contains a component-step-
ping identifier at reset, i.e.
in Intel386 DX CPU, DH
e
3 indicates Intel386
DX CPU after reset
DL
e
revision number;
in Intel386 SX CPU, DH
e
23H indicates
Intel386 SX CPU after reset
DL
e
revision number.
79
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