參數(shù)資料
型號(hào)： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁(yè)數(shù)： 52/102頁(yè)
文件大?。?/td> 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
If NA
Y
is sampled active, the Intel386 SX Micro-
processor is free to drive the address and bus cycle
definition of the next bus cycle, and assert ADS
Y
,
as soon as it has a bus request internally pending. It
may drive the next address as early as the next bus
state, whether the current bus cycle is acknowl-
edged at that time or not.
Regarding the details of address pipelining, the
Intel386 SX Microprocessor has the following char-
acteristics:
1. The next address may appear as early as the bus
state after NA
Y
was sampled active (see Figures
5.9 or 5.10). In that case, state T2P is entered
immediately. However, when there is not an inter-
nal bus request already pending, the next address
will not be available immediately after NA
Y
is as-
serted and T2I is entered instead of T2P (see Fig-
ure 5.11 Cycle 3). Provided the current bus cycle
isn’t yet acknowledged by READY
Y
asserted,
T2P will be entered as soon as the Intel386 SX
Microprocessor does drive the next address. Ex-
ternal hardware should therefore observe the
ADS
Y
output as confirmation the next address is
actually being driven on the bus.
2. Any address which is validated by a pulse on the
ADS
Y
output will remain stable on the address
pins for at least two processor clock periods. The
Intel386 SX Microprocessor cannot produce a
new address more frequently than every two
processor clock periods (see Figures 5.9, 5.10,
and 5.11).
3. Only the address and bus cycle definition of the
very next bus cycle is available. The pipelining ca-
pability cannot look further than one bus cycle
ahead (see Figure 5.11 Cycle 1).
240187–25
Following any bus state (Ti) the address is always non-pipelined and NA
Y
is only sampled during wait states. To start
address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (cycle 1 above)
The pipelined cycles (2, 3, 4 above) are shown with various numbers of wait states.
Figure 5.10. Fastest Transition to Pipelined Address Following Idle Bus State
52
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