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參數(shù)資料
| 型號： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 63/102頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
5.5 Self-test Signature
Upon completion of self-test (if self-test was re-
quested by driving BUSY
Y
LOW at the falling edge
of RESET) the EAX register will contain a signature
of 00000000H indicating the Intel386 SX Microproc-
essor passed its self-test of microcode and major
PLA contents with no problems detected. The pass-
ing signature in EAX, 00000000H, applies to all revi-
sion levels. Any non-zero signature indicates the unit
is faulty.
5.6 Component and Revision
Identifiers
To assist users, the Intel386 SX Microprocessor af-
ter reset holds a component identifier and revision
identifier in its DX register. The upper 8 bits of DX
hold 23H as identification of the Intel386 SX Micro-
processor (the lower nibble, 03H, refers to the
Intel386 DX Architecture. The upper nibble, 02H, re-
fers to the second member of the Intel386 DX Fami-
ly). The lower 8 bits of DX hold an 8-bit unsigned
binary number related to the component revision
level. The revision identifier will, in general, chrono-
logically track those component steppings which are
intended to have certain improvements or distinction
from previous steppings. The Intel386 SX Microproc-
essor revision identifier will track that of the Intel386
DX CPU where possible.
The revision identifier is intended to assist users to a
practical extent. However, the revision identifier val-
ue is not guaranteed to change with every stepping
revision, or to follow a completely uniform numerical
sequence, depending on the type or intention of re-
vision, or manufacturing materials required to be
changed. Intel has sole discretion over these char-
acteristics of the component.
Table 5.7. Component and
Revision Identifier History
Stepping
Revision Identifier
A0
B
C
D
E
04H
05H
08H
08H
08H
5.7 Coprocessor Interfacing
The Intel386 SX Microprocessor provides an auto-
matic interface for the Intel Intel387 SX numeric
floating-point coprocessor. The Intel387 SX coproc-
essor uses an I/O mapped interface driven automat-
ically by the Intel386 SX Microprocessor and assist-
ed by three dedicated signals: BUSY
Y
, ERROR
Y
and PEREQ.
As the Intel386 SX Microprocessor begins support-
ing a coprocessor instruction, it tests the BUSY
Y
and ERROR
Y
signals to determine if the coproces-
sor can accept its next instruction. Thus, the
BUSY
Y
and ERROR
Y
inputs eliminate the need for
any ‘preamble’ bus cycles for communication be-
tween processor and coprocessor. The Intel387 SX
can be given its command opcode immediately. The
dedicated signals provide instruction synchroniza-
tion, and eliminate the need of using the WAIT op-
code (9BH) for Intel387 SX instruction synchroniza-
tion (the WAIT opcode was required when the 8086
or 8088 was used with the 8087 coprocessor).
Custom coprocessors can be included in Intel386
SX Microprocessor based systems by memory-
mapped or I/O-mapped interfaces. Such coproces-
sor interfaces allow a completely custom protocol,
and are not limited to a set of coprocessor protocol
‘primitives’.
Instead,
memory-mapped
mapped interfaces may use all applicable instruc-
tions for high-speed coprocessor communication.
The BUSY
Y
and ERROR
Y
inputs of the Intel386
SX Microprocessor may also be used for the custom
coprocessor interface, if such hardware assist is de-
sired. These signals can be tested by the WAIT op-
code (9BH). The WAIT instruction will wait until the
BUSY
Y
input is inactive (interruptable by an NMI or
enabled INTR input), but generates an exception 16
fault if the ERROR
Y
pin is active when the BUSY
Y
goes (or is) inactive. If the custom coprocessor inter-
face is memory-mapped, protection of the address-
es used for the interface can be provided with the
Intel386 SX CPU’s on-chip paging or segmentation
mechanisms. If the custom interface is I/O-mapped,
protection of the interface can be provided with the
IOPL (I/O Privilege Level) mechanism.
or
I/O-
The Intel387 SX numeric coprocessor interface is
I/O mapped as shown in Table 5.8. Note that the
Intel387 SX coprocessor interface addresses are
beyond the 0H-0FFFFH range for programmed I/O.
When the Intel386 SX Microprocessor supports the
Intel387 SX coprocessor, the Intel386 SX Micro-
processor automatically generates bus cycles to the
coprocessor interface addresses.
Table 5.8. Numeric Coprocessor Port Addresses
Address in Intel386 SX
CPU I/O Space
Intel387 SX
Coprocessor Register
8000F8H
8000FCH/8000FEH
*
*
Generated as 2nd bus cycle during Dword transfer.
Opcode Register
Operand Register
To correctly map the Intel387 SX registers to the
appropriate I/O addresses, connect the CMD0 and
CMD1 lines of the Intel387 SX as listed in Table 5.9.
Table 5.9. Connections for CMD0
and CMD1 Inputs for the Intel387 SX
Signal
Connection
CMD0
Connect directly
to Intel386 SX CPU A2 signal
Connect to ground.
CMD1
63
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