參數(shù)資料
型號(hào)： KU386
廠商： Intel Corp.
英文描述： SX MICROPROCESSOR
中文描述： SX微處理器
文件頁(yè)數(shù)： 50/102頁(yè)
文件大小： 1268K
代理商： KU386
Intel386
TM
SX MICROPROCESSOR
Non-Pipelined Address
Any bus cycle may be performed with non-pipelined
address timing. For example, Figure 5.6 shows a
mixture of read and write cycles with non-pipelined
address timing. Figure 5.6 shows that the fastest
possible cycles with non-pipelined address have two
bus states per bus cycle. The states are named T1
and T2. In phase one of T1, the address signals and
bus cycle definition signals are driven valid and, to
signal their availability, address strobe (ADS
Y
) is
simultaneously asserted.
During read or write cycles, the data bus behaves as
follows. If the cycle is a read, the Intel386 SX Micro-
processor floats its data signals to allow driving by
the external device being addressed.
The Intel386
SX Microprocessor requires that all data bus
pins be at a valid logic state (HIGH or LOW) at
the end of each read cycle, when READY
Y
is
asserted. The system MUST be designed to
meet this requirement.
If the cycle is a write, data
signals are driven by the Intel386 SX Microproces-
sor beginning in phase two of T1 until phase one of
the bus state following cycle acknowledgment.
Figure 5.7 illustrates non-pipelined bus cycles with
one wait state added to Cycles 2 and 3. READY
Y
is
sampled inactive at the end of the first T2 in Cycles
2 and 3. Therefore Cycles 2 and 3 have T2 repeated
again. At the end of the second T2, READY
Y
is
sampled active.
When address pipelining is not used, the address
and bus cycle definition remain valid during all wait
states. When wait states are added and it is desir-
able to maintain non-pipelined address timing, it is
necessary to negate NA
Y
during each T2 state ex-
cept the last one, as shown in Figure 5.7 Cycles 2
and 3. If NA
Y
is sampled active during a T2 other
than the last one, the next state would be T2I or T2P
instead of another T2.
When address pipelining is not used, the bus states
and transitions are completely illustrated by Figure
5.8. The bus transitions between four possible
states, T1, T2, T
i
, and T
h
. Bus cycles consist of T1
and T2, with T2 being repeated for wait states. Oth-
erwise the bus may be idle, T
i
, or in the hold ac-
knowledge state T
h
.
240187–23
Bus States:
T1Dfirst clock of a non-pipelined bus cycle (Intel386
TM
SX CPU drives new address and asserts ADS
Y
).
T2Dsubsequent clocks of a bus cycle when NA
Y
has not been sampled asserted in the current bus cycle.
TiDidle state.
ThDhold acknowledge state (Intel386 SX CPU asserts HLDA).
The fastest bus cycle consists of two states T1 and T2.
Four basic bus states describe bus operation when not using pipelined address.
Figure 5.8. Bus States (not using pipelined address)
50
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