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參數(shù)資料
| 型號： | KU386 |
| 廠商： | Intel Corp. |
| 英文描述： | SX MICROPROCESSOR |
| 中文描述： | SX微處理器 |
| 文件頁數(shù)： | 41/102頁 |
| 文件大?。?/td> | 1268K |
| 代理商： | KU386 |
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Intel386
TM
SX MICROPROCESSOR
ADDRESS BUS (A
23
–A
1
, BHE
Y
, BLE
Y
)
These three-state outputs provide physical memory
addresses or I/O port addresses. A
23
–A
16
are LOW
during I/O transfers except for I/O transfers auto-
matically generated by coprocessor instructions.
During coprocessor I/O transfers, A
22
–A
16
are driv-
en LOW, and A
23
is driven HIGH so that this ad-
dress line can be used by external logic to generate
the coprocessor select signal. Thus, the I/O address
driven by the Intel386 SX Microprocessor for co-
processor commands is 8000F8H, the I/O address-
es driven by the Intel386 SX Microprocessor for co-
processor data are 8000FCH or 8000FEH for cycles
to the Intel387
TM
SX.
The address bus is capable of addressing 16 mega-
bytes of physical memory space (000000H through
FFFFFFH), and 64 kilobytes of I/O address space
(000000H through 00FFFFH) for programmed I/O.
The address bus is active HIGH and will float during
bus hold acknowledge.
The Byte Enable outputs, BHE
Y
and BLE
Y
, directly
indicate which bytes of the 16-bit data bus are in-
volved with the current transfer. BHE
Y
applies to
D
15
–D
8
and BLE
Y
applies to D
7
–D
0
. If both BHE
Y
and BLE
Y
are asserted, then 16 bits of data are
being transferred. See Table 5.1 for a complete de-
coding of these signals. The byte enables are active
LOW and will float during bus hold acknowledge.
BUS CYCLE DEFINITION SIGNALS
(W/R
Y
, D/C
Y
, M/IO
Y
, LOCK
Y
)
These three-state outputs define the type of bus cy-
cle being performed: W/R
Y
distinguishes between
write and read cycles, D/C
Y
distinguishes between
data and control cycles, M/IO
Y
distinguishes be-
tween memory and I/O cycles, and LOCK
Y
distin-
guishes between locked and unlocked bus cycles.
All of these signals are active LOW and will float
during bus acknowledge.
The primary bus cycle definition signals are W/R
Y
,
D/C
Y
and M/IO
Y
, since these are the signals driv-
en valid as ADS
Y
(Address Status output) becomes
active. The LOCK
Y
is driven valid at the same time
the bus cycle begins, which due to address pipelin-
ing, could be after ADS
Y
becomes active. Exact bus
cycle definitions, as a function of W/R
Y
, D/C
Y
, and
M/IO
Y
are given in Table 5.2.
LOCK
Y
indicates that other system bus masters are
not to gain control of the system bus while it is ac-
tive. LOCK
Y
is activated on the CLK2 edge that be-
gins the first locked bus cycle (i.e., it is not active at
the same time as the other bus cycle definition pins)
and is deactivated when ready is returned at the end
of the last bus cycle which is to be locked. The be-
ginning of a bus cycle is determined when READY
Y
is returned in a previous bus cycle and another is
pending (ADS
Y
is active) or by the clock edge in
which ADS
Y
is driven active if the bus was idle. This
means that it follows more closely with the write
data rules when it is valid, but may cause the bus to
be locked longer than desired. The LOCK
Y
signal
may be explicitly activated by the LOCK prefix on
certain instructions. LOCK
Y
is always asserted
when executing the XCHG instruction, during de-
scriptor updates, and during the interrupt acknowl-
edge sequence.
Table 5.1. Byte Enable Definitions
BHE
Y
BLE
Y
Function
0
0
1
1
0
1
0
1
Word Transfer
Byte transfer on upper byte of the data bus, D
15
–D
8
Byte transfer on lower byte of the data bus, D
7
–D
0
Never occurs
Table 5.2. Bus Cycle Definition
M/IO
Y
D/C
Y
W/R
Y
Bus Cycle Type
Locked
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Interrupt Acknowledge
does not occur
I/O Data Read
I/O Data Write
Memory Code Read
Halt:
Address
e
2
BHE
Y
e
1
BLE
Y
e
0
Memory Data Read
Memory Data Write
Yes
D
No
No
No
No
Shutdown:
Address
e
0
BHE
Y
e
1
BLE
Y
e
0
1
1
1
1
0
1
Some Cycles
Some Cycles
41
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