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| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 107/162頁 |
| 文件大小： | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
49
7.3.2
KBI Pin Enable Register (KBIPE)
KBIPE contains the pin enable control bits.
7.3.3
KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.
7.4
Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was designed to simplify the
connection and use of row-column matrices of keyboard switches. However, these inputs are also useful as extra external
interrupt inputs and as an external means of waking the MCU from stop or wait low-power modes.
The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPEn bits in the keyboard interrupt
pin enable register (KBIPE) independently enables or disables each KBI pin. Each KBI pin can be configured as edge sensitive
or edge and level sensitive based on the KBMOD bit in the keyboard interrupt status and control register (KBISC). Edge sensitive
can be software programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or edge
and level sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs must be at the reset logic level.
A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the reset level) during one bus cycle and
then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 during
one bus cycle and then a logic 1 during the next cycle.
7.4.1
Edge Only Sensitivity
A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the
CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC.
7
6
5
4
3
2
1
0
R
KBIPE7
KBIPE6
KBIPE5
KBIPE4
KBIPE3
KBIPE2
KBIPE1
KBIPE0
W
Reset:
0
Figure 7-3 KBI Pin Enable Register
Table 7-3 KBIPE Register Field Descriptions
Field
Description
7:0
KBIPEn
Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin.
0
Pin not enabled as keyboard interrupt.
1
Pin enabled as keyboard interrupt.
7
6
5
4
3
2
1
0
R
KBEDG7
KBEDG6
KBEDG5
KBEDG4
KBEDG3
KBEDG2
KBEDG1
KBEDG0
W
Reset:
0
Figure 7-4 KBI Edge Select Register
Table 7-4 KBIES Register Field Descriptions
Field
Description
7:0
KBEDGn
Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level
function of the corresponding pin).
0
Falling edge/low level.
1
Rising edge/high level.
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