MPXY8300 Series
Sensors
Freescale Semiconductor
13
3.5.5
LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If
the LVD is enabled by setting the LVDE and the LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the
voltage regulator remains active during stop mode. If the user attempts to enter either stop1 or stop2 with the LVD enabled in
stop (LVDSE = 1), the MCU will enter stop4 instead.
3.5.6
Active BDM Enabled in Stop Mode
Entry into the active background debug mode from run mode is enabled if the ENBDM bit in BDCSCR is set. The BDCSCR
register is not memory mapped so it can only be accessed through the BDM interface by use of the BDM commands
READ_STATUS and WRITE_CONTROL. If ENBDM is set when the CPU executes a STOP instruction, the system clocks to the
background debug logic remain active when the MCU enters stop mode so background debug communication is still possible.
In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation (stop4 mode).
If the user attempts to enter either stop1 or stop2 with ENDBM set, the MCU will enter stop4 with system clocks running.
Most background commands are not available in stop mode. The memory-access-with-status commands do not allow memory
access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be
used to wake the MCU from stop and enter active background mode if the ENDBM bit is set. Once in background debug mode,
all background commands are available. The table below summarizes the behavior of the MCU in stop mode when entry into the
background debug mode is enabled.
3.5.7
MCU On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules except the wake-up timer and LFR
detectors/decoder are stopped. Even in the exception case (ENDBM = 1), where clocks are kept alive to the background debug
logic, clocks to the peripheral systems are halted to reduce power consumption.
I/O Pins (Optional PTA0:3)
The I/O pin states remain unchanged when the MCU enters stop3 or stop4 mode.
If the MCU is configured to go into stop2 mode, the I/O pin states are latched before entering stop2.
If the MCU is configured to go into stop1 mode, the I/O pins are forced to their default reset state
(Hi-Z) upon entry into stop1.
Memory
All RAM and register contents are preserved while the MCU is in stop3 or stop4 mode.
All registers will be reset upon wake-up from stop2, but the contents of RAM are preserved and pin states remain latched
until the PPDACK bit is written. The user may save any memory-mapped register data into RAM before entering stop2 and
restore the data upon exit from stop2.
All registers will be reset upon wake-up from stop1 and the contents of RAM are not preserved. The MCU must be initialized
as upon reset. The contents of the FLASH memory are non-volatile and are preserved in any of the stop modes.
Parameter Registers
The 32 bytes of parameter registers are kept active in all modes of operation as long as power is applied to the supply pins.
The contents of the parameter registers behave like RAM and are unaffected by any reset.
LFO
The LFO remains active regardless of any mode of operation.
MFO
The medium frequency oscillator (MFO) will remain powered up when the MCU enters the stop mode if the LFR detector is
periodically sampled or a pressure or acceleration measurement has been initiated.
CFO
The CFO can be activated in any of the stop modes, but will shut itself off after the selected TCHG delay.
HFO
The HFO is halted in all stop modes.
PWU
The PWU remains active regardless of any mode of operation.
ADC10
If the asynchronous internal ADC10 clock is not selected as the conversion clock, entering the stop3 or stop4 mode aborts
the existing conversion and places the ADC10 in its idle state. After exiting from stop mode, a write to the ADSC1 register
is required to resume conversions.