參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 99/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
Freescale Semiconductor
41
5.9.9
System Power Management Status and Control 1 Register (SPMSC1)
Figure 5-11 System Power Management Status and Control 1 Register (SPMSC1)
5.9.10
System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop mode behavior of the MCU.
7
6
5
4
3
2
1(1)
NOTES:
1. Bit 1 is a reserved bit that must always be written to 0.
0
R
LVDF
0
LVDIE
LVDRE(2)
2. This bit can be written only one time after reset. Additional writes are ignored.
LVDSE
LVDE(2)
BGBE
W
LVDACK
Reset:
0
1
0
= Unimplemented or Reserved
Table 5-14 SPMSC1 Register Field Descriptions
Field
Description
7
LVDF
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return logic 0.
5
LVDIE
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0
Hardware interrupt disabled (use polling)
1
Request a hardware interrupt when LVDF = 1
4
LVDRE
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0
LVDF does not generate hardware resets
1
Force an MCU reset when LVDF = 1
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-volt-
age detect function operates when the MCU is in stop mode.
0
Low-voltage detect disabled during stop mode
1
Low-voltage detect enabled during stop mode
2
LVDE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0
LVD logic disabled
1
LVD logic enabled
0
BGBE
Bandgap Buffer Enable — The BGBE bit is used to enable an internal buffer for the bandgap voltage refer-
ence for use by the ADC module on one of its internal channels.
0
Bandgap buffer disabled
1
Bandgap buffer enabled
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