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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 132/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
71
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow.
An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when
the first counter overflow will occur.
9.3.4
Timer x Channel n Status and Control Register (TPMCnSC)
TPMCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel
configuration, and pin function.
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
Figure 9-6 Timer x Counter Modulo Register Low (TPMMODL)
7
6
5
4
3
2
1
0
R
CHnF
CHnIE
MSnB
MSnA
ELSnB
ELSnA
0
W
Reset
0
= Unimplemented or Reserved
Figure 9-7 Timer x Channel n Status and Control Register (TPMCnSC)
Table 9-4 TPMCnSC Register Field Descriptions
Field
Description
7
CHnF
Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge
occurs on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set
when the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag
is seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPMCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a pre-
vious CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0
No input capture or output compare event occurred on channel n
1
Input capture or output compare event occurred on channel n
6
CHnIE
Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0
Channel n interrupt requests disabled (use software polling)
1
Channel n interrupt requests enabled
5
MSnB
Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for edge-
aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 9-5.
4
MSnA
Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for
input capture mode or output compare mode. Refer to Table 9-5 for a summary of channel mode and setup
controls.
3:2
ELSn[B:A]
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MSnB:MSnA and shown in Table 9-5, these bits select the polarity of the input edge that triggers an
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any
timer channel functions. This function is typically used to temporarily disable an input capture channel or to
make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a soft-
ware timer that does not require the use of a pin.
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