- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224792 > PPXY8300A6T1 (FREESCALE SEMICONDUCTOR INC) DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT PDF資料下載
參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 32/162頁(yè) |
| 文件大小： | 4316K |
| 代理商： | PPXY8300A6T1 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)
MPXY8300 Series
Sensors
Freescale Semiconductor
127
programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate
power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target
system reset or otherwise disturbing the running application program.
Figure 15-1 BDM Tool Connector
15.2.1
BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication
of active background mode commands and data. During reset, this pin is used to select between starting in active background
mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host
development tool to determine the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This
protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All
communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time.
Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer
to Section 15.2.2.
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent
to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pull-up so no external pull-up resistor is required. Unlike typical open-
drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal
rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking
harmful drive level conflicts. Refer to Section 15.2.2, for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pull-up on BKGD chooses normal
operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after
reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this
Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug
interface.
15.2.2
Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each
bit time. The external controller provides this falling edge whether data is transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first
at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from
the host. Any BDC command that was in progress when this time-out occurs is aborted without affecting the memory or operating
mode of the target MCU system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The
BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of
these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC
clock signal is shown for reference in counting cycles.
Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous
to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of
the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives
the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive
the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this
period.
2
4
6
NO CONNECT 5
NO CONNECT 3
1
RESET
BKGD
GND
VDD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PR35MT2 | RECTANGULAR ADAPTER |
| PR406-BCR5HD | T-1 3/4 SINGLE COLOR LED, RED, 4.6 mm |
| PR44-PCG28H-CG | SINGLE COLOR LED, GREEN, 6.35 mm |
| PRADA1-07F-BR000 | ROCKER SWITCH, DPST, LATCHED, 7A, PANEL MOUNT |
| PRADD1-07F-BB000 | ROCKER SWITCH, DPST, LATCHED, 7A, PANEL MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPYY12C0.75 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket Material:PVC (Polyvinyl Chloride), External Diameter:9.9mm, |
| PPYY12C0.75 100M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 100M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Met 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Metric):100m, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket , RoHS Compliant: Yes |
| PPYY12C0.75 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 50M |
| PPYY12C1.50 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, PER M |
| PPYY12C1.50 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, 50M |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。