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參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 32/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
127
programmed. Sometimes VDD can be used to allow the pod to use power from the target system to avoid the need for a separate
power supply. However, if the pod is powered separately, it can be connected to a running target system without forcing a target
system reset or otherwise disturbing the running application program.
Figure 15-1 BDM Tool Connector
15.2.1
BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for bidirectional serial communication
of active background mode commands and data. During reset, this pin is used to select between starting in active background
mode or starting the user’s application program. This pin is also used to request a timed sync response pulse to allow a host
development tool to determine the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of microcontrollers. This
protocol assumes the host knows the communication clock rate that is determined by the target BDC clock rate. All
communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time.
Commands and data are sent most significant bit first (MSB first). For a detailed description of the communications protocol, refer
to Section 15.2.2.
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC command may be sent
to the target MCU to request a timed sync response signal from which the host can determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pull-up so no external pull-up resistor is required. Unlike typical open-
drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal
rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking
harmful drive level conflicts. Refer to Section 15.2.2, for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pull-up on BKGD chooses normal
operating mode. When a debug pod is connected to BKGD it is possible to force the MCU into active background mode after
reset. The specific conditions for forcing active background depend upon the HCS08 derivative (refer to the introduction to this
Development Support section). It is not necessary to reset the target MCU to communicate with it through the background debug
interface.
15.2.2
Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to indicate the start of each
bit time. The external controller provides this falling edge whether data is transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data is transferred MSB first
at 16 BDC clock cycles per bit (nominal speed). The interface times out if 512 BDC clock cycles occur between falling edges from
the host. Any BDC command that was in progress when this time-out occurs is aborted without affecting the memory or operating
mode of the target MCU system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the BDC clock source. The
BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams show timing for each of
these cases. Interface timing is synchronous to clocks in the target BDC, but asynchronous to the external host. The internal BDC
clock signal is shown for reference in counting cycles.
Figure 15-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU. The host is asynchronous
to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of
the bit time. Ten target BDC clock cycles later, the target senses the bit level on the BKGD pin. Typically, the host actively drives
the pseudo-open-drain BKGD pin during host-to-target transmissions to speed up rising edges. Because the target does not drive
the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this
period.
2
4
6
NO CONNECT 5
NO CONNECT 3
1
RESET
BKGD
GND
VDD
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| PPYY12C0.75 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket Material:PVC (Polyvinyl Chloride), External Diameter:9.9mm, |
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