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參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 20/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
116
Freescale Semiconductor
13.6.5
PLL Control Registers A- PLLCR0:1
The PLLCR0:1 registers contain 13 control bits for the RFX as described in Figure 13-13. This register is accessed by writing to
the RFX register address $04 and $05 using the SPI.
Table 13-7 RFX Transmit Control Register Field Descriptions
Field
Description
7
SEND
Transmission Start Command — The SEND control bit starts the transmission of data held in the RFX data
buffer according to the bit length specified by the FRM bits. The SEND control bit is automatically cleared when
the data buffer transmission has ended or by a RFX reset.
0
Data transmission ended or transmission not in progress
1
Start data transmission or transmission in progress
6
RFEF
RF Transmission Error Flag — The RFEF status bit indicates if there was an error in the current of prior RF
transmission as described in Section 13.5.4. The RFEF status bit is cleared by writing a logical one to the SEND
bit or by a RFX reset.
0
No RF transmission error occurred
1
RF transmission error occurred
5
RCTS
RF Ready to Send — The RCTS status bit indicates if the VCO and PLL have started and locked and the RFX
is ready to send transmit data as described in Section 13.2.2. The RCTS status bit is cleared by a RFX reset.
0
RFX not ready to send data
1
RFX ready to send data
4-0
PWR[4:0]
RF Amplifier Power Level — The PWR control bits select the optimum power output of the RF power ampli-
fier. These power output levels assume optimal matching network to the RF pin. The PWR control bits are
cleared by a RFX reset.
The PWR control bits should normally be set to $0E. This nominal setting is targeting +5 dBm power output
including the matching network loss. The LSB corresponds to a tuning of approximately 0.5 dBm and allows the
user to optimize the RF link and power consumption. It can also be used to compensate the temperature and
voltage variation in power output. Note that settings above nominal setting of $0E, the output power amplifier
compression is limiting the effective output power.
$04
Bit 7
6
5
4
3
2
1
Bit 0
R
AFREQ[12:5]
W
RESET:
0
$05
R
AFREQ[4:0]
1
0
W
RESET:
0
1
0
Figure 13-13 PLL Control Registers A (PLLCR0:1)
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