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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 24/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
12
Freescale Semiconductor
3.5.2
Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and the current state of all
of the I/O pins.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other memory-mapped
registers which they want to restore after exit of stop2, to locations in RAM. Upon exit of stop2, these values can be restored by
user software before the I/O pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned off, except for the
RAM. The voltage regulator is placed in a low-power standby state, as is the ADC10. Upon entry into stop2, the states of the I/O
pins are latched.
Exit from stop2 is done by asserting either a reset or interrupt function to the MCU.
Upon wake-up from stop2 mode, the MCU will start up the same as from a power-on reset (POR) except the I/O pin states remain
latched by taking the reset vector. The system and all peripherals will be in their default reset states and must be initialized. After
waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to go to a stop2 recovery routine.
PPDF remains set and the I/O pin states remain latched until a logic 1 is written to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the contents of the I/O port
registers, which have been saved in RAM, to the port registers before writing to the PPDACK bit. If the port registers are not
restored from RAM before writing to PPDACK, then the register bits will assume their default reset states when the I/O pin latches
are opened and the I/O pins will switch to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that interfaces to the pin before
writing to the PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their
associated port control registers when the I/O latches are opened.
3.5.3
Stop3 Mode
Upon entering the stop3 mode, all of the clocks in the MCU except the LFO are halted. The voltage regulator and the ADC10
enter into their standby states. The states of all of the internal registers and logic, as well as the RAM content, are maintained.
The I/O pin states are not latched at the pin as in stop2. Instead they are maintained by virtue of the fact that the states of the
internal logic driving the pins are being maintained.
Exit from stop3 is done by asserting either a reset or interrupt function to the MCU. If caused by a reset the MCU will be reset
and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will
result in the MCU taking the appropriate interrupt vector.
3.5.4
Stop4 Mode
Stop4 is identical to stop3 except that full regulation is maintained which results in higher power consumption.
LFR Detector(2)
Periodically On
LFR Decoder
On
RFX Charge Pump
Optionally On
RFX Data Buffer, Encoder
On
RFX Transmitter(3)
Optionally On
ADC10
Off
Standby
Optionally On(4)
SPI
Off
Standby
Regulator
Off
Standby
On
I/O Pins
Hi-Z
States Held
Wake-Up Methods
Interrupts, resets
NOTES:
1. MFO oscillator started if the LFR detectors are periodically sampled, the LFR detectors detect an input signal; or a pressure
or acceleration reading is in progress.
2. Period of sampling set by MCU.
3. RF data buffer may be set up to run while the CPU is in the stop modes.
4. Requires internal ADC10 clock to be enabled.
Table 3-1 Stop Mode Behavior (Continued)
Mode
Stop1
Stop2
Stop3
Stop4
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