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參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 38/162頁 |
| 文件大小： | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
132
Freescale Semiconductor
write data bus, the RWAEN and RWA control bits have an additional purpose, in full address plus data comparisons they are
used to decide which of these buses to use in the comparator B data bus comparisons. If RWAEN = 1 (enabled) and RWA = 0
(write), the CPU’s write data bus is used. Otherwise, the CPU’s read data bus is used.
The currently selected trigger mode determines what the debugger logic does when a comparator detects a qualified match
condition. A match can cause:
Generation of a breakpoint to the CPU
Storage of data bus values into the FIFO
Starting to store change-of-flow addresses into the FIFO (begin type trace)
Stopping the storage of change-of-flow addresses into the FIFO (end type trace)
15.3.2
Bus Capture Information and FIFO Operation
The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO
has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was
stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it. If
a trace run is manually halted by writing 0 to ARM before the FIFO is full (CNT = 1:0:0:0), the information is shifted by one position
and the host must perform ((8 – CNT) – 1) dummy reads of the FIFO to advance it to the first significant entry in the FIFO.
In most trigger modes, the information stored in the FIFO consists of 16-bit change-of-flow addresses. In these cases, read
DBGFH then DBGFL to get one coherent word of information out of the FIFO. Reading DBGFL (the low-order byte of the FIFO
data port) causes the FIFO to shift so the next word of information is available at the FIFO data port. In the event-only trigger
modes (see Section 15.3.5), 8-bit data information is stored into the FIFO. In these cases, the high-order half of the FIFO
(DBGFH) is not used and data is read out of the FIFO by simply reading DBGFL. Each time DBGFL is read, the FIFO is shifted
so the next data value is available through the FIFO data port at DBGFL.
In trigger modes where the FIFO is storing change-of-flow addresses, there is a delay between CPU addresses and the input
side of the FIFO. Because of this delay, if the trigger event itself is a change-of-flow address or a change-of-flow address appears
during the next two bus cycles after a trigger event starts the FIFO, it will not be saved into the FIFO. In the case of an end-trace,
if the trigger event is a change-of-flow, it will be saved as the last change-of-flow entry for that debug run.
The FIFO can also be used to generate a profile of executed instruction addresses when the debugger is not armed. When
ARM = 0, reading DBGFL causes the address of the most-recently fetched opcode to be saved in the FIFO. To use the profiling
feature, a host debugger would read addresses out of the FIFO by reading DBGFH then DBGFL at regular periodic intervals.
The first eight values would be discarded because they correspond to the eight DBGFL reads needed to initially fill the FIFO.
Additional periodic reads of DBGFH and DBGFL return delayed information about executed instructions so the host debugger
can develop a profile of executed instruction addresses.
15.3.3
Change-of-Flow Information
To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the
normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target
system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow
information stored in the FIFO.
For conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the
address of the conditional branch opcode). Because BRA and BRN instructions are not conditional, these events do not cause
change-of-flow information to be stored in the FIFO.
Indirect JMP and JSR instructions use the current contents of the H:X index register pair to determine the destination address,
so the debug system stores the run-time destination address for any indirect JMP or JSR. For interrupts, RTI, or RTS, the
destination address is stored in the FIFO as change-of-flow information.
15.3.4
Tag vs. Force Breakpoints and Triggers
Tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other
action until and unless that instruction is actually executed by the CPU. This distinction is important because any change-of-flow
from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to
be thrown away without being executed.
A force-type breakpoint waits for the current instruction to finish and then acts upon the breakpoint request. The usual action in
response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application
program.
The tag vs. force terminology is used in two contexts within the debug module. The first context refers to breakpoint requests
from the debug module to the CPU. The second refers to match signals from the comparators to the debugger control logic. When
a tag-type break request is sent to the CPU, a signal is entered into the instruction queue along with the opcode so that if/when
this opcode ever executes, the CPU will effectively replace the tagged opcode with a BGND opcode so the CPU goes to active
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