參數(shù)資料
型號: PPXY8300A6T1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: Pressure Sensor
英文描述: DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝: SOIC-20
文件頁數(shù): 115/162頁
文件大?。?/td> 4316K
代理商: PPXY8300A6T1
MPXY8300 Series
Sensors
56
Freescale Semiconductor
is forced to remain active when the MCU enters stop mode. In this case, if a serial BACKGROUND command is issued to the
MCU through the background debug interface while the CPU is in stop mode, CPU clocks will resume and the CPU will enter
active background mode where other serial background commands can be processed. This ensures that a host development
system can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the
Section 3 for more details.
8.4.5
BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in normal user programs
because it forces the CPU to stop processing user instructions and enter the active background mode. The only way to resume
execution of the user program is through reset or by a host debug system issuing a GO, TRACE1, or TAGGO serial command
through the background debug interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When
the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user
program.
8.5
HCS08 Instruction Set Summary
Instruction Set Summary Nomenclature
The nomenclature listed here is used in the instruction descriptions in Table 8-2.
Operators
( )
=
Contents of register or memory location shown inside parentheses
=
Is loaded with (read: “gets”)
&
=
Boolean AND
|
=
Boolean OR
=
Boolean exclusive-OR
×
=
Multiply
÷
=
Divide
:
=
Concatenate
+=
Add
=
Negate (two’s complement)
CPU registers
A
=
Accumulator
CCR
=
Condition code register
H
=
Index register, higher order (most significant) 8 bits
X
=
Index register, lower order (least significant) 8 bits
PC
=
Program counter
PCH
=
Program counter, higher order (most significant) 8 bits
PCL
=
Program counter, lower order (least significant) 8 bits
SP
=
Stack pointer
Memory and addressing
M
=
A memory location or absolute data, depending on addressing mode
M:M + 0x0001
=
A 16-bit value in two consecutive memory locations. The higher-order (most significant) 8 bits are
located at the address of M, and the lower-order (least significant) 8 bits are located at the next higher
sequential address.
Condition code register (CCR) bits
V
=
Two’s complement overflow indicator, bit 7
H
=
Half carry, bit 4
I
=
Interrupt mask, bit 3
N
=
Negative indicator, bit 2
Z
=
Zero indicator, bit 1
C
=
Carry/borrow, bit 0 (carry out of bit 7)
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