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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 37/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
131
The SYNC command is unlike other BDC commands because the host does not necessarily know the correct communications
speed to use for BDC communications until after it has analyzed the response to the SYNC command.
To issue a SYNC command, the host:
Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest clock is normally the
reference oscillator/64 or the self-clocked rate/64.)
Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically one cycle of the fastest
clock in the system.)
Removes all drive to the BKGD pin so it reverts to high impedance
Monitors the BKGD pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal
BDC communications):
Waits for BKGD to return to a logic high
Delays 16 cycles to allow the host to stop driving the high speedup pulse
Drives BKGD low for 128 BDC clock cycles
Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent BDC
communications. Typically, the host can determine the correct communication speed within a few percent of the actual target
speed and the communication protocol can easily tolerate speed errors of several percent.
15.2.4
BDC Hardware Breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a 16-bit match value in the
BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged breakpoint. A forced breakpoint causes the
CPU to enter active background mode at the first instruction boundary following any access to the breakpoint address. The
tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the CPU will enter active
background mode rather than executing that instruction if and when it reaches the end of the instruction queue. This implies that
tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any
address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to enable the breakpoint
logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the breakpoint logic is disabled and no BDC breakpoints
are requested regardless of the values in other BDC breakpoint registers and control bits. The force/tag select (FTS) control bit
in BDCSCR is used to select forced (FTS = 1) or tagged (FTS = 0) type breakpoints.
The on-chip debug module (DBG) includes circuitry for two additional hardware breakpoints that are more flexible than the simple
breakpoint in the BDC module.
15.3
On-Chip Debug System (DBG)
Because HCS08 devices do not have external address and data buses, the most important functions of an in-circuit emulator
have been built onto the chip with the MCU. The debug system consists of an 8-stage FIFO that can store address or data bus
information, and a flexible trigger system to decide when to capture bus information and what information to capture. The system
relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage
FIFO.
The debug module includes control and status registers that are accessible in the user’s memory map. These registers are
located in the high register space to avoid using valuable direct page memory space.
Most of the debug module’s functions are used during development, and user programs rarely access any of the control and
status registers for the debug module. The one exception is that the debug system can provide the means to implement a form
of ROM patching. This topic is discussed in greater detail in Section 15.3.6.
15.3.1
Comparators A and B
Two 16-bit comparators (A and B) can optionally be qualified with the R/W signal and an opcode tracking circuit. Separate control
bits allow you to ignore R/W for each comparator. The opcode tracking circuitry optionally allows you to specify that a trigger will
occur only if the opcode at the specified address is actually executed as opposed to only being read from memory into the
instruction queue. The comparators are also capable of magnitude comparisons to support the inside range and outside range
trigger modes. Comparators are disabled temporarily during all BDC accesses.
The A comparator is always associated with the 16-bit CPU address. The B comparator compares to the CPU address or the 8-
bit CPU data bus, depending on the trigger mode selected. Because the CPU data bus is separated into a read data bus and a
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