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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 21/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
117
13.6.6
PLL Control Registers B- PLLCR2:3
The PLLCR2:3 registers contain 13 control bits for the RFX as described in Figure 13-14. This register is accessed by writing to
the RFX register address $04 and $05 using the SPI.
Table 13-8 PLL Control Registers A Field Descriptions
Field
Description
$04 [7-0]
$05 [7-3]
AFREQ
[12:0]
PLL Divider Ratio A — The AFREQ control bits select the PLL divider ratio for a data zero in the FSK mode of
modulation as described by the following equation:
Where:
fCARRIER = RF Carrier frequency in MHz
fXTAL
=
External crystal frequency in MHz
AFREQ
=
Decimal value of the AFREQ binary weighted bits
The AFREQ control bits are cleared by a RFX reset.
$05 [2]
Set to 1
This bit must always be set to a 1 when writing to the PLLCR1 register.
$05 [1-0]
Set to 0
These bits must always be set to a 0 when writing to the PLLCR1 register.
$06
Bit 7
6
5
4
3
2
1
Bit 0
R
BFREQ12
BFREQ11
BFREQ10
BFREQ9
BFREQ8
BFREQ7
BFREQ6
BFREQ5
W
RESET:
0
$07
R
BFREQ4
BFREQ3
BFREQ2
BFREQ1
BFREQ0
CF
MOD
CKREF
W
RESET:
0
Figure 13-14 PLL Control Registers B (PLLCR2:3)
Table 13-9 PLL Control Registers B Field Descriptions
Field
Description
$06 [7-0]
$07 [7-3]
BFREQ
[12:0]
PLL Divider Ratio B — The BFREQ control bits select the PLL divider ratio for a data one in either the ASK or
FSK modes of modulation as described by the following equation:
where:
fCARRIER = RF Carrier frequency in MHz
fXTAL
=
External crystal frequency in MHz
BFREQ
=
Decimal value of the BFREQ binary weighted bits
The BFREQ control bits are cleared by a RFX reset.
$07 [2]
CF
Carrier Frequency — The CF control bit selects the optimal VCO setup and correct divider for the 500 kHz ref-
erence clock to the MCU on DX based on the external crystals required for the desired carrier frequency. For
either carrier frequency the external crystal must also be selected as shown in. The CF control bit is cleared by
a RFX reset.
0
Configured for 315 MHz, PLL Divider Ratio (fRF/fXTAL) = 19.6713, required external crystal = 16.0132 MHz
1
Configured for 434 MHz, PLL Divider Ratio (fRF/fXTAL) = 19.6713, required external crystal = 22.0586 MHz
f
CARRIER
f
XTAL
19
AFREQ
8192
----------------------
+
×
=
f
CARRIER
f
XTAL
19
BFREQ
8192
----------------------
+
×
=
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