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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 90/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
33
5.5
Low-Voltage Detect (LVD) System
The MPXY8300 Series includes a system to detect low voltage conditions in order to protect memory contents and control MCU
system states during supply voltage variations. The system is comprised of a power-on reset (POR) circuit and an LVD circuit
with a user selectable trip voltage, either high (VLVDH) or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high
and the trip voltage is selected by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE
bit is set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current consumption in stop3 with
the LVD enabled will be greater.
5.5.1
Power-On Reset Operation
When power is initially applied to the device, or when the supply voltage drops below the VPOR level, the POR circuit will cause
a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the VLVDL
level. Both the POR bit and the LVD bit in SRS are set following a POR.
5.5.2
LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDRE to 1. After an LVD
reset has occurred, the LVD system will hold the device in reset until the supply voltage has risen above the level determined by
LVDV. The LVD bit in the SRS register is set following either an LVD reset or POR.
5.5.3
LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE set, LVDIE set, and
LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.5.4
Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is approaching, but is still above,
the LVD voltage. The LVW does not have an interrupt associated with it. There are two user selectable trip voltages for the LVW,
one high (VLVWH) and one low (VLVWL). The trip voltage is selected by LVWV in SPMSC2.
5.6
System Clock Control
There are three clock sources within the MPXY8300 series MCU:
Internal high frequency oscillator (HFO) with nominal frequency of 8 MHz
Internal medium frequency oscillator (MFO) with nominal frequency of 125 kHz
Internal low frequency oscillator (LFO) with nominal frequency of 1 kHz
The internal MCU bus clock is derived from the HFO and is
1/2, 1/4, 1/8, or 1/16 of the HFO frequency, as set by the BUSCLKS
bits in SOPT2. The MFO feeds the HFO with a reference clock. Both the MFO and HFO are enabled when the MCU is in run or
wait mode. Additionally, the MFO can be turned on and off by the LF receiver module (LFR). The LFO is used by the RTI and the
PWU and runs continuously in all MCU modes: run, wait, stop4, stop3, stop2, and stop1.
The BUSCLKS control bits select the clock frequency of the HFO as given in Table 5-3. These bits are cleared by any MCU reset.
5.7
Real-Time Interrupt (RTI)
The RTI uses either the internal low frequency oscillator (LFO) or the high frequency oscillator output as its clock source. The
RTICLKS bit determines which clock is selected. The RTI can be used as a periodic interrupt in MCU run mode, or can be used
as a periodic wake-up from all low power modes. The LFO is always active and cannot be powered off by any software control.
The HFO clock cannot be used in any stop mode because it will be disabled.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control value
(RTIS2:RTIS1:RTIS0) used to select one of seven wake-up periods between 2 ms and 128 ms. The RTI has a local interrupt
Table 5-3 HFO Frequency Selections
BUSCLKS1
BUSCLKS0
HFO Frequency
(MHz)
CPU Bus Frequency
(MHz)
0
1
0.5
0
1
2
1
0
4
2
1
8
4
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