參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 129/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
Freescale Semiconductor
69
Each timer channel has:
An 8-bit status and control register (TPMCnSC)
A 16-bit channel value register (TPMCnVH:TPMCnVL)
Refer to the direct-page register summary in the Section 4 of this data sheet for the absolute address assignments for all TPM
registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used
to translate these names into the appropriate absolute addresses.
Some MCU systems have more than one TPM, so register names include placeholder characters to identify which TPM and
which channel is being referenced. For example, TPMxCnSC refers to timer (TPM) x, channel n and TPM1C2SC is the status
and control register for timer 1, channel 2.
9.3.1
Timer x Status and Control Register (TPMSC)
TPMSC contains the overflow status flag and control bits that are used to configure the interrupt enable, TPM configuration, clock
source, and prescale divisor. These controls relate to all channels within this timer module.
7
6
5
4
3
2
1
0
R
TOF
TOIE
CPWMS
CLKSB
CLKSA
PS2
PS1
PS0
W
Reset
0
= Unimplemented or Reserved
Figure 9-2 Timer x Status and Control Register (TPMSC)
Table 9-2 TPMSC Register Field Descriptions
Field
Description
7
TOF
Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set
after the counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If
another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would
remain set after the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF
has no effect.
0
TPM counter has not reached modulo value or overflow
1
TPM counter has overflowed
6
TOIE
Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
0
TOF interrupts inhibited (use software polling)
1
TOF interrupts enabled
5
CPWMS
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Set-
ting CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears
CPWMS.
0
All TPM channels operate as input capture, output compare, or edge-aligned PWM mode as selected by
the MSnB:MSnA control bits in each channel’s status and control register
1
All TPM channels operate in center-aligned PWM mode
4:3
CLKS[B:A]
Clock Source Select — As shown in Table 9-1, this 2-bit field is used to disable the TPM system or select one
of three clock sources to drive the counter prescaler. The internal DX source is synchronized to the bus clock by
an on-chip synchronization circuit.
2:0
PS[2:0]
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in
Table 9-3. This prescaler is located after any clock source synchronization or clock source selection, so it
affects whatever clock source is selected to drive the TPM system.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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