參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 131/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
70
Freescale Semiconductor
9.3.2
Timer x Counter Registers (TPMCNTH:TPMCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter. Reading either byte
(TPMCNTH or TPMCNTL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read.
This allows coherent 16-bit reads in either order. The coherency mechanism is automatically restarted by an MCU reset, a write
of any value to TPMCNTH or TPMCNTL, or any write to the timer status/control register (TPMSC).
Reset clears the TPM counter registers.
When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain
in the state they were in when the background mode became active even if one or both bytes of the counter are read while
background mode is active.
9.3.3
Timer x Counter Modulo Registers (TPMMODH:TPMMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo
value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down (CPWMS = 1),
and the overflow flag (TOF) becomes set. Writing to TPMMODH or TPMMODL inhibits TOF and overflow interrupts until the other
byte is written. Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo
disabled).
Table 9-3 Prescale Divisor Selection
PS2:PS1:PS0
TPM Clock Source Divided-By
0:0:0
1
0:0:1
2
0:1:0
4
0:1:1
8
1:0:0
16
1:0:1
32
1:1:0
64
1:1:1
128
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Any write to TPMCNTH clears the 16-bit counter.
Reset
0
Figure 9-3 Timer x Counter Register High (TPMCNTH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Any write to TPMCNTL clears the 16-bit counter.
Reset
0
Figure 9-4 Timer x Counter Register Low (TPMCNTL)
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
0
Figure 9-5 Timer x Counter Modulo Register High (TPMMODH)
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