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| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 93/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
36
Freescale Semiconductor
5.9.3
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as WRITE_BYTE must be used to write
to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.
Figure 5-4 System Background Debug Force Reset Register (SBDFR)
Table 5-5 SRS Register Field Descriptions
Field
Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred
while the internal supply was below the LVR threshold.
0
Reset not caused by POR
1
POR caused reset
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0
Reset came from external reset pin
1
Reset not caused by external reset pin
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source may be blocked by COPE = 0.
0
Reset not caused by COP time-out
1
Reset caused by COP time-out
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0
Reset not caused by an illegal opcode
1
Reset caused by an illegal opcode
3
ILAD
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimple-
mented memory address.
0
Reset not caused by an illegal address
1
Reset caused by an illegal address
2
PWU
Programmable Wakeup — Reset was caused by a PWU reset in run, wait, stop4, and stop3. After stop2 or
stop1 exit, PRF in PWUCSI indicates PWU was the source of a wake-up.
0
Reset not caused by PWU.
1
Reset caused by PWU.
1
LVD
Low Voltage Detect — If the LVDRE and LVDSE bits are set and the supply drops below the LVD trip voltage,
an LVD reset will occur. This bit is also set by POR.
0
Reset not caused by LVD trip or POR.
1
Reset caused by LVD trip or POR.
7
6
5
4
3
2
1
0
R
0
W
BDFR(1)
NOTES:
1. BDFR is writable only through serial background debug commands, not from user programs.
Reset:
0
= Unimplemented or Reserved
Table 5-6 SBDFR Register Field Descriptions
Field
Description
0
BDFR
Background Debug Force Reset — A serial background command such as WRITE_BYTE may be used to
allow an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit
cannot be written from a user program.
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