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| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 40/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
134
Freescale Semiconductor
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin,
the CPU will execute an SWI instruction instead of going to active background mode.
15.4
Register Definition
This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments
for all DBG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file is used to translate these names into the appropriate absolute addresses.
15.4.1
BDC Registers and Control Bits
The BDC has two registers:
The BDC status and control register (BDCSCR) is an 8-bit register containing control and status bits for the background
debug controller.
The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU
(so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written at any time. For
example, the ENBDM control bit may not be written while the MCU is in active background mode. (This prevents the ambiguous
condition of the control bit forbidding active background mode while the MCU is already in active background mode.) Also, the
four status bits (BDMACT, WS, WSF, and DVF) are read-only status indicators and can never be written by the
WRITE_CONTROL serial BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
15.4.1.1
BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL) but is not accessible to
user programs because it is not located in the normal memory map of the MCU.
7
6
5
4
3
2
1
0
R
ENBDM
BDMACT
BKPTEN
FTS
CLKSW
WS
WSF
DVF
W
Normal Reset
0
Reset in
Active BDM:
1
0
1
0
= Unimplemented or Reserved
Figure 15-5 BDC Status and Control Register (BDCSCR)
Table 15-2 BDCSCR Register Field Descriptions
Field
Description
7
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a nor-
mal reset clears it.
0
BDM cannot be made active (non-intrusive commands still allowed)
1
BDM can be made active to allow active background mode commands
6
BDMACT
Background Mode Active Status — This is a read-only status bit.
0
BDM not active (user application program running)
1
BDM active and waiting for serial commands
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0
BDC breakpoint disabled
1
BDC breakpoint enabled
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