參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 42/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
136
Freescale Semiconductor
Figure 15-6 System Background Debug Force Reset Register (SBDFR)
15.4.3
DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers.
These registers are located in the high register space of the normal memory map so they are accessible to normal application
programs. These registers are rarely if ever accessed by normal user application programs with the possible exception of a ROM
patching mechanism that uses the breakpoint logic.
15.4.3.1
Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is forced to 0x00 at reset and
can be read at any time or written at any time unless ARM = 1.
15.4.3.2
Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is forced to 0x00 at reset and
can be read at any time or written at any time unless ARM = 1.
15.4.3.3
Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is forced to 0x00 at reset and
can be read at any time or written at any time unless ARM = 1.
15.4.3.4
Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is forced to 0x00 at reset and
can be read at any time or written at any time unless ARM = 1.
15.4.3.5
Debug FIFO High Register (DBGFH)
This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have no meaning or effect.
In the event-only trigger modes, the FIFO only stores data into the low-order byte of each FIFO word, so this register is not used
and will read 0x00.
Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the FIFO, read DBGFH
before reading DBGFL because reading DBGFL causes the FIFO to advance to the next word of information.
15.4.3.6
Debug FIFO Low Register (DBGFL)
This register provides read-only access to the low-order eight bits of the FIFO. Writes to this register have no meaning or effect.
Reading DBGFL causes the FIFO to shift to the next available word of information. When the debug module is operating in event-
only modes, only 8-bit data is stored into the FIFO (high-order half of each FIFO word is unused). When reading 8-bit words out
of the FIFO, simply read DBGFL repeatedly to get successive bytes of data from the FIFO. It isn’t necessary to read DBGFH in
this case.
Do not attempt to read data from the FIFO while it is still armed (after arming but before the FIFO is filled or ARMF is cleared)
because the FIFO is prevented from advancing during reads of DBGFL. This can interfere with normal sequencing of reads from
the FIFO.
7
6
5
4
3
2
1
0
R
0
W
BDFR(1)
NOTES:
1. BDFR is writable only through serial background mode debug commands, not from user programs.
Reset
0
= Unimplemented or Reserved
Table 15-3 SBDFR Register Field Description
Field
Description
0
BDFR
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE
allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit
cannot be written from a user program.
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