參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 137/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
76
Freescale Semiconductor
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the transition from the value set in the
modulus register to 0x0000. When the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter
changes direction at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
9.5.3
Channel Event Interrupt Description
The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned
PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any
edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is
set. The flag is cleared by the 2-step sequence described in Section 9.5.1.
When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches
the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 9.5.1.
9.5.4
PWM End-of-Duty-Cycle Events
For channels that are configured for PWM operation, there are two possibilities:
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the
channel value register that marks the end of the active duty cycle period.
When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice
during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle,
which are the times when the timer counter matches the channel value register.
The flag is cleared by the 2-step sequence described in Section 9.5.1.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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