- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224792 > PPXY8300A6T1 (FREESCALE SEMICONDUCTOR INC) DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT PDF資料下載
參數(shù)資料
| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 114/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁當前第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁
MPXY8300 Series
Sensors
Freescale Semiconductor
55
8.4
Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like other CPU instructions.
In addition, a few instructions such as STOP and WAIT directly affect other MCU circuitry. This section provides additional
information about these operations.
8.4.1
Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer operating properly)
watchdog, or by assertion of an external active-low reset pin. When a reset event occurs, the CPU immediately stops whatever
it is doing (the MCU does not wait for an instruction boundary before responding to a reset event). For a more detailed discussion
about how the MCU recognizes resets and determines the source, refer to the Section 5.
The reset event is considered concluded when the sequence to determine whether the reset came from an internal source is
done and when the reset pin is no longer asserted. At the conclusion of a reset event, the CPU performs a 6-cycle sequence to
fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for execution of the first program
instruction.
8.4.2
Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the
program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt.
The CPU responds to an interrupt by performing the same sequence of operations as for a software interrupt (SWI) instruction,
except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt
sequence started.
The CPU sequence for an interrupt is:
1.
Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2.
Set the I bit in the CCR.
3.
Fetch the high-order half of the interrupt vector.
4.
Fetch the low-order half of the interrupt vector.
5.
Delay for one free bus cycle.
6.
Fetch three bytes of program information starting at the address indicated by the interrupt vector to fill the instruction
queue in preparation for execution of the first instruction in the interrupt service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt
service routine. Although it is possible to clear the I bit with an instruction in the interrupt service routine, this would allow nesting
of interrupts (which is not recommended because it leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) is not saved on the stack
as part of the interrupt sequence. The user must use a PSHH instruction at the beginning of the service routine to save H and
then use a PULH instruction just before the RTI that ends the interrupt service routine. It is not necessary to save H if you are
certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change
the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the global I bit in the CCR and
it is associated with an instruction opcode within the program so it is not asynchronous to program execution.
8.4.3
Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the CPU to reduce overall
power consumption while the CPU is waiting for the interrupt or reset event that will wake the CPU from wait mode. When an
interrupt or reset event occurs, the CPU clocks will resume and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in wait mode,
CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be
processed. This ensures that a host development system can still gain access to a target MCU even if it is in wait mode.
8.4.4
Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power
consumption. In such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake-
up the target MCU when it is time to resume processing. Unlike the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be
configured to keep a minimum set of clocks running in stop mode. This optionally allows an internal periodic signal to wake the
target MCU from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control bit has been set by a
serial command through the background interface (or because the MCU was reset into active background mode), the oscillator
相關PDF資料 |
PDF描述 |
|---|---|
| PR35MT2 | RECTANGULAR ADAPTER |
| PR406-BCR5HD | T-1 3/4 SINGLE COLOR LED, RED, 4.6 mm |
| PR44-PCG28H-CG | SINGLE COLOR LED, GREEN, 6.35 mm |
| PRADA1-07F-BR000 | ROCKER SWITCH, DPST, LATCHED, 7A, PANEL MOUNT |
| PRADD1-07F-BB000 | ROCKER SWITCH, DPST, LATCHED, 7A, PANEL MOUNT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPYY12C0.75 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket Material:PVC (Polyvinyl Chloride), External Diameter:9.9mm, |
| PPYY12C0.75 100M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 100M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Met 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Metric):100m, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket , RoHS Compliant: Yes |
| PPYY12C0.75 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 50M |
| PPYY12C1.50 | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, PER M |
| PPYY12C1.50 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, 50M |
發(fā)布緊急采購，3分鐘左右您將得到回復。