參數(shù)資料
型號: PPXY8300A6T1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: Pressure Sensor
英文描述: DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝: SOIC-20
文件頁數(shù): 68/162頁
文件大小: 4316K
代理商: PPXY8300A6T1
MPXY8300 Series
Sensors
16
Freescale Semiconductor
4.2
Reset and Interrupt Vectors
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used
in the equate file provided by Freescale in the Codewarrior project file.
4.3
Register Addresses and Bit Assignments
The registers in the MPXY8300 Series are divided into these four groups:
Direct-page registers are located in the first 64 locations in the memory map; these are accessible with efficient direct
addressing mode instructions.
The parameter registers begin at address $0040; these are also accessible with efficient direct addressing mode
instructions.
High-page registers are used less often, so they are located above $1800 in the memory map. This leaves more room
in the direct page for more frequently used registers and variables.
The nonvolatile register area consists of a block of 16 locations in FLASH memory at $FFB0:FFBF. Nonvolatile register
locations include:
Three values that are loaded into working registers at reset
An 8-byte backdoor comparison key that optionally allows the user to gain controlled access to secure memory.
Because the nonvolatile register locations are FLASH memory, they must be erased and programmed like other FLASH
memory locations.
Direct page registers are located within the first 256 locations in the memory map, so they are accessible with efficient direct
addressing mode instructions, which requires only the lower byte of the address. Bit manipulation instructions can be used to
access any bit in any direct-page register. Table 4-2 is a summary of all user-accessible direct-page registers and control bits.
Those related to the TPMS application and modules are described in detail in this specification.
The register names in the second column of the table are shown in bold to set them apart from the bit names to the right. Cells
that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0. Shaded
cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
Table 4-1 Vector Summary
Vector Addr
(High/Low)
Module
Source
Vector
Name
$DFE0:DFE1
KBI
Vkbi
$DFE2:DFE3
PCI
Vpci
$DFE4:DFE5
ACI
Vacc
$DFE6:DFE7
Sys Ctrl
Vrti
$DFE8:DFE9
LFR
Vlfrcvr
$DFEA:DFEB
ADC10
Vadc1
$DFEC:DFED
Reserved
$DFEE:DFEF
SPI
Vspi1
$DFF0:DFF1
TPM1
Vtpm1ovf
$DFF2:DFF3
TPM1
Vtpm1ch1
$DFF4:DFF5
TPM1
Vtpm1ch0
$DFF6:DFF7
PWU
Vwuktmr
$DFF8:DFF9
Sys Ctrl
Vlvd
$DFFA:DFFB
Reserved
$DFFC:DFFD
SWI opcode
Vswi
$DFFE:DFFF
Sys Ctrl - POR
Vreset
Sys Ctrl - PRF
Sys Ctrl - COP
Sys Ctrl - LVD
Temp Restart
Illegal opcode
Illegal address
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