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| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁(yè)數(shù)： | 92/162頁(yè) |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
35
5.9.2
System Reset Status Register (SRS)
This register includes seven read-only status flags to indicate the source of the most recent reset. When a debug host forces
reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS will be set. Writing any value to this register
address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on
what caused the MCU to reset.
Figure 5-3 System Reset Status (SRS)
Table 5-4 IRQSC Register Field Descriptions
Field
Description
5
IRQEDG
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or lev-
els on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensi-
tive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured to
detect rising edges, the optional pull-up resistor is re-configured as an optional pull-down resistor.
0
IRQ is falling edge or falling edge/low-level sensitive.
1
IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request. Also, when this bit is set, either an internal pull-up or an internal pull-down
resistor is enabled depending on the state of the IRQMOD bit.
0
IRQ pin function is disabled.
1
IRQ pin function is enabled.
3
IRQF
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0
No IRQ request.
1
IRQ event detected.
2
IRQACK
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear
IRQF). Writing 0 has no meaning or effect. Reads always return logic 0. If edge-and-level detection is selected
(IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate a hardware inter-
rupt request.
0
Hardware interrupt requests from IRQF disabled (use polling).
1
Hardware interrupt requested whenever IRQF = 1.
0
IRQMOD
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level detec-
tion. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt request
events.
0
IRQ event on falling edges or rising edges only.
1
IRQ event on falling edges and low levels or on rising edges and high levels.
7
6
5
4
3
2
1
0
R
POR
PIN
COP
ILOP
ILAD
PWU
LVD
0
W
Reset:
Writing any value to SIMRS address clears COP watchdog timer.
Power-on reset:
1
0
1
0
Low-voltage reset:
1
0
1
0
Any other reset:
0
((1))
NOTES:
1. Any of these reset sources that are active at the time of reset will cause the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset will be cleared.
(1)
0
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