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| 型號： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 133/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
72
Freescale Semiconductor
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to
get an unexpected indication of an edge trigger. Typically, a program would clear status flags after changing channel configuration
bits and before enabling channel interrupts or using the status flags to avoid any unexpected behavior.
9.3.5
Timer x Channel Value Registers (TPMCnVH:TPMCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for
the output compare or PWM functions. The channel value registers are cleared by reset.
In input capture mode, reading either byte (TPMCnVH or TPMCnVL) latches the contents of both bytes into a buffer where they
remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMCnSC
register is written.
In output compare or PWM modes, writing to either byte (TPMCnVH or TPMCnVL) latches the value into a buffer. When both
bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching
mechanism may be manually reset by writing to the TPMCnSC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.
9.4
Functional Description
All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor.
A 16-bit modulo register also is associated with the main 16-bit counter in the TPM. Each TPM channel is optionally associated
with an MCU pin and a maskable interrupt function.
Table 9-5 Mode, Edge, and Level Selection
CPWMS
MSnB:MSnA
ELSnB:ELSnA
Mode
Configuration
X
XX
00
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
0
00
01
Input capture
Capture on rising edge only
10
Capture on falling edge only
11
Capture on rising or falling edge
01
00
Output compare Software compare only
01
Toggle output on compare
10
Clear output on compare
11
Set output on compare
1X
10
Edge-aligned
PWM
High-true pulses (clear output on compare)
X1
Low-true pulses (set output on compare)
1
XX
10
Center-aligned
PWM
High-true pulses (clear output on compare-up)
X1
Low-true pulses (set output on compare-up)
7
6
5
4
3
2
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Reset
0
Figure 9-8 Timer x Channel Value Register High (TPMCnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
Figure 9-9 Timer Channel Value Register Low (TPMCnVL)
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