Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
135
Agere Systems Inc.
9 SPE Mapper Registers
Table of Contents
Contents
Page
9 SPE Mapper Registers .................................................................................................................................. 135
9.1 SPE Mapper Register Descriptions ...........................................................................................................136
9.2 SPE Mapper Register Map ........................................................................................................................153
Tables
Page
Table 154. SPE_VERSION_R, SPE Version and Identification Register (RO).....................................................136
Table 155. SPE_ONESHOT, One Shot (R/W) ......................................................................................................136
Table 156. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW).....................................................136
Table 157. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) ..................................................................................138
Table 158. SPE_STATE1—SPE_STATE2, Receive/Transmit State and Value Parameters (RO)........................140
Table 159. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Rx Control for Alarm and OH Functions (R/W) .................141
Table 160. SPE_CNTD1—SPE_CNTD2, Continuous N-Times Detect Values (R/W) ..........................................142
Table 161. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W)................................................143
Table 162. SPE_RMON1—SPE_RMON5, Receive Monitor Values (RO)............................................................143
Table 163. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) ..........................143
Table 164. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W)..........................146
Table 165. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W) .........................................148
Table 166. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W) ............................................................148
Table 167. SPE_TOHINS1—SPE_TOHINS4, Transmit OH Insert Value (R/W)...................................................149
Table 168. SPE_SIGDEG_CTL1—SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W)....149
Table 169. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W) ............150
Table 170. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess Zero Error Count (RO)..150
Table 171. SPE_PTRCNT1—SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO) ............151
Table 172. SPE_RJ1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO).....................................151
Table 173. SPE_TJ1DINS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W) .....................................151
Table 174. SPE_RJ1DEXP_R1—SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W).............................151
Table 175. SPE_SCRATCH_R, Scratch Pad (R/W)..............................................................................................151
Table 176. SPE_SPE_RX_THRES_CTL_DS3, Receive Elastic Store Threshold Control for DS3 (R/W)............152
Table 177. SPE_SPE_TX_THRES_CTL_DS3, Transmit Elastic Store Threshold Control for DS3 (R/W) ...........152
Table 178. SPE_SPE_OV_UN_FIFO_THRES FIFO Overflow and Underflow Thresholds (R/W)........................152
Table 179. SPE Mapper Register Map..................................................................................................................153