TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
548
Agere Systems Inc.
21 28-Channel Framer Block Functional Description
(continued)
21.29 Superframer Register Addressing
Table 621
summarizes the address map for the global and per-link/channel registers of the superframer:
Table 621. Framer Addressing Map for the Global and Per-Link/Channel Registers of the Superframer
21.29.1 Per Link Register Sections in the Above Table
SIG = Signaling (see
Section 12.9.1, Signaling Per Link Registers, on page 272
).
PM = Performance Monitor (see
Section 12.3, Performance Monitor Global Registers, on page 250
).
RDL = Receive (Facility) Data Link (see
Section 12.11, Receive Facility Data Link Configuration and Status Registers, on
page 293
).
TDL = Transmit (Facility) Data Link (see
Section 12.12, Transmit Facility Data Link Configuration and Status Registers,
on page 295
).
SYS = System Interface (see
Section 12.13, System Interface, Arbiter, and Frame Formatter Mapping, on page 298
).
AR = Arbiter (Framer) (see
Section 12.2, Arbiter (Framer) Global Registers, on page 248
).
FF = Frame Formatter (Transmit Framer) (see
Section 12.16, Frame Formatter Per Link Registers, on page 305
).
LC = Line Encoder/Decoders (see
Section 12.18, Line Encoder/Decoder Per Link Registers, on page 308
); RXP = 0 for
the line encoder and TXP = 1 for the line decoder.
HDLC = High-Level Data Link Control (see
Section 12.19, HDLC Per Channel Configuration and Status Registers, on
page 309
); RXP = 0 for the receive HDLC and TXP = 1 for the transmit HDLC.
RXP = High-Level Data Link Control (see
Table 444 on page 309
) RXP = 0 for the receive HDLC and TXP = 1 for the
transmit HLDLC.
Address Pins (ADDR15—ADDR0)
8
7
Framer Global Registers
RXP = 0/
TXP = 1
0
0
0
0
0
0
0
15
0
14
13
12
11
10
9
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Superframer Global
AR (Framer)
Performance Monitor
Performance Monitor
HDLC
System Interface
Signaling
Frame Formatter
(Transmit Framer)
Reserved
Receive Data Link
Transmit Data Link
Reserved
1
1
1
1
0
0
0
0
0
1
0
1
0
Others
0
Links 1—28 (00001—11100)
LNK4 LNK3 LNK2 LNK1 LNK0
Framer Functional Register Addresses
SIG6
SIG5
SIG4
0
PM5
PM4
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
SIG3
PM3
RDL3
TDL3
0
0
0
1
1
SIG2
PM2
RDL2
TDL2
SYS2
0
1
0
1
SIG1
PM1
RDL1
TDL1
SYS1
AR1
FF1
Res.
LC1
SIG0
PM0
RDL0
TDL0
SYS0
AR0
FF0
Res.
LC0
1
HDLC Channels 1—64 (000000—111111)
HDL9 HDL8 HDL7 HDL6 HDL5
RXP = 0/
TXP = 1
Per-Channel Register
HDL3
HDL2
HDL4
HDL1
HDL0