Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
445
Agere Systems Inc.
19 VT/TU Mapper Functional Description
(continued)
I
Trace identifier mismatch (TIM-V) will be detected following the number of consecutively errored sequences
(1-byte or 16-byte sequences) programmed in bits
VT_
J2_NTIME[3:0] (
Table 196 on page 165
), and reported to
the microprocessor via bit VT_J2TIM[1—28] (
Table 190 on page 163
). If TIM-V is detected, the J2 byte monitor
will transition into the capture mode and start searching for two consecutive consistent 1-byte or 16-byte
sequences. Once two consecutive consistent sequences are detected, the J2 byte monitor will transition into the
monitor mode and start searching for the number of consecutive mismatches programmed in register bits
VT_
J2_NTIME[3:0] on a per 1-byte or 16-byte sequence basis.
Once the hardware finds synchronization
(
VT_
J2TIM[1—28] = 0), the new sequence is latched into
VT_
J2BYTE_DET[1—28][1—16][7:0] (
Table 222 on
page 174
). The synchronization algorithm used will not allow single bit errors to pass through to
VT_
J2BYTE_DET[1—28][1—16][7:0].
I
Unless bit
VT_
J2TIM_AIS_INH (
Table 194 on page 164
) is set to a 1,
VT_
J2TIM[1—28] will contribute to auto-
matic AIS generation.
I
Any change in state of
VT_
J2TIM[1—28][1—16][7:0] will be reported in bit
VT_
J2TIM_D[1—28] (
Table 182 on
page 159
). Unless the
VT_
J2TIM_M[1—28] (
Table 186 on page 161
) mask bit is set,
VT_
J2TIM_D[1—28] = 1
will generate an interrupt.
19.12 Receive Signaling (RX_VTSIG)
The RX_VTSIG logic block (in
Figure 40 on page 435
) will perform all necessary functions to extract and transmit
the received signaling bits when operating in DS1 byte-synchronous mode. The following features are imple-
mented:
I
The signaling is sent to the appropriate framer link selected by bits VT_RXSIG_CH_SEL[1—28][4:0] (
Table 217
on page 172
). VT_RXSIG_CH_SEL[1—28][4:0] is a necessary duplication of the routing information pro-
grammed within the cross connect (XC) block.
I
When VT_SYNC_PBIT[1—28] = 1 (
Table 217 on page 172
), the RX_VTSIG block will synchronize to the incom-
ing VT/TU phase indication (P1, P0). Otherwise, VT_LOPS[1—28] (
Table 190 on page 163
) and
VT_LOPS_D[1—28] (
Table 182 on page 159
) will be forced to 0.
I
P-bit phase synchronization (VT_LOPS[1—28] = 0) is declared following two consecutive nonerrored multi-
frames (48 frames). Loss of phase synchronization (VT_LOPS[1—28] = 1) is declared following the number of
consecutive errored multiframes programmed in bits VT_LOPS_NTIME[3:0] (
Table 195 on page 165
). Any
change in VT_LOPS[1—28] state will be detected and reported to the microprocessor with bit VT_LOPS_D[1—
28].
I
If the loss of phase synchronization (VT_LOPS[1—28] = 1) condition exists and VT_LOPS_AIS_INH = 0, DS1
AIS is transmitted downstream and the signaling bits will be forced to the value in SMPR_OH_DEFLT (
Table 77
on page 70
) in the MPU block. Otherwise (VT_LOPS[1—28] = 0), the VT_RX_VTSIG logic block will behave as
described in
Table 568
.
I
Unless VT_LOPS_M[1—28] (
Table 186 on page 161
) mask bit is set, VT_LOPS_D[1—28] will generate an inter-
rupt.
I
See
Table 568
for signaling behavior based on the receive status and control.