Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
77
Agere Systems Inc.
8 TMUX Registers
Table of Contents
Contents
Page
8 TMUX Registers ............................................................................................................................................... 77
8.1 TMUX Register Descriptions........................................................................................................................79
8.2 TMUX Register Map...................................................................................................................................126
Tables
Page
Table 87. TMUX_ID_R, TMUX Identification Register (RO)....................................................................................79
Table 88. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W)....................................................................79
Table 89. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W) ............................................................79
Table 90. TMUX_TX_DLT, Delta/Event (COR/COW) ..............................................................................................80
Table 91. TMUX_RPS_DLT, Delta/Event (COR/COW)............................................................................................80
Table 92. TMUX_RHS_DLT, Delta/Event (COR/COW) ...........................................................................................81
Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)...............................................................................83
Table 94. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0).............................89
Table 95. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)..........................90
Table 96. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)..........................90
Table 97. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0)....................91
Table 98. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0).............93
Table 99. TMUX_TX_STATE, State Parameters (RO) ............................................................................................93
Table 100. TMUX_RPS_STATE, State and Value Parameters (RO).......................................................................93
Table 101. TMUX_RHS_STATE, State and Value Parameters (RO) ......................................................................94
Table 102. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO)..........................................................94
Table 103. TMUX_RHS_CTL, Receive High-Speed Control Parameters (R/W).....................................................96
Table 104. TMUX_RLS_BITBLK_CTL, Receive Low-Speed Control Parameters (R/W)........................................96
Table 105. TMUX_RLS_MODE_CTL, Receive Low-Speed Control Parameters (R/W) .........................................97
Table 106. TMUX_RAISINH_CTL, Receive Low-Speed Control Parameters (R/W)...............................................98
Table 107. TMUX_LOSDETCNT, Receive Low-Speed Control Parameters (R/W).................................................99
Table 108. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W) ........................100
Table 109. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W)........................101
Table 110. TMUX_C2EXP[1—2_3], Continuous N-Times Detect Control Parameters (R/W)...............................102
Table 111. TMUX_RF1MON, Receive Monitor Values (RO)..................................................................................102
Table 112. TMUX_RAPSMON, Receive Monitor Values (RO) ..............................................................................102
Table 113. TMUX_RS1MON, Receive Monitor Values (RO).................................................................................102
Table 114. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO)..........................................................103
Table 115. TMUX_TLS_CTL, Transmit Low-Speed Control Parameters (R/W)....................................................104
Table 116. TMUX_THS_PORT_CTL, Transmit High-Speed Port Control Parameters (R/W)...............................105
Table 117. TMUX_THS_TOH_CTL, Transmit High-Speed Control Parameters (R/W).........................................105
Table 118. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) ...............................107
Table 119. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W) ................................ 111
Table 120. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W)............................... 111
Table 121. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W)..................................................112
Table 122. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W)...........................................112
Table 123. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W)...............................................112
Table 124. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W) ................................112
Table 125. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)..................114
Table 126. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W).................115
Table 127. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)................................115
Table 128. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W).............................117