TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
212
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
Table 248. M13_DS1_AIS_DETD_R[1—4], DS1 Alarm Indication Signal Delta Registers (RO)
Table 249. M13_DS1_LB_DETD_R[1—4], DS1 Loopback Detect Delta Registers (RO)
Table 250. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO)
Table 251. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10022
0x10023
—
0x10025
0x10022
0x10023
0x10024
0x10025
15:4
15:8
RSVD
RSVD
Reserved
.
Reserved
.
3:0
7:0
7:0
7:0
M13_DS1_AIS_DETD[28:25]
M13_DS1_AIS_DETD[24:17]
M13_DS1_AIS_DETD[16:9]
M13_DS1_AIS_DETD[8:1]
Delta Bits.
These individual delta bits are set as the
result of the corresponding state bits
M13_DS1_AIS_DET[28:1] (
Table 260 on page 215
)
transitioning either from 0 to 1 or from 1 to 0. Delta
bits can be programmed to be either clear on read
(COR) or clear on write (COW), and they are not set
to 1 again until the event reoccurs.
0x00
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10026
0x10027
—
0x10029
0x10026
0x10027
0x10028
0x10029
15:4
15:8
RSVD
RSVD
Reserved.
Reserved.
3:0
7:0
7:0
7:0
M13_DS1_LB_DETD[28:25]
M13_DS1_LB_DETD[24:17]
M13_DS1_LB_DETD[16:9]
M13_DS1_LB_DETD[8:1]
Delta Bits.
These individual delta bits are set as the
result of the corresponding state bits
M13_DS1_LB_DET[28:1] (
Table 261 on page 215
)
transitioning either from 0 to 1 or from 1 to 0. Delta
bits can be programmed to be either clear on read
(COR) or clear on write (COW), and they are not set
to 1 again until the event reoccurs.
0x00
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x1002F
15:7
6:0
RSVD
Reserved
.
M13_XC_DS2_LOC[7:1] A logic 1 of M13_XC_DS2_LOCy bit indicates that loss of
clock is detected on the DS2 clock input.
Address
Bit
Name
Function
Reset
Default
0x000
0x00
0x10030
15:7
6:0
RSVD
Reserved
.
M13_XC_DS2_AIS_DET[7:1]
M13_XC_DS2_AIS_DETy Bit.
The
M13_XC_DS2_AIS_DETy bit is set high if the input
XC_DS2M23DATAy is 0 for fewer than 5 clock cycles
in each of two consecutive 840 clock periods, and
cleared if there are more than four zeros in each of two
consecutive 840-bit periods.