TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
450
Agere Systems Inc.
19 VT/TU Mapper Functional Description
(continued)
V5 Overhead Byte Format/Generation.
The V5 overhead byte will be mapped as defined in
Table 571
.
Table 571. V5 Overhead Byte Format
The following features are supported:
I
When operating in tributary loopback mode (bit VT_LB_SEL[1—28] = 1 (
Table 211 on page 170
)), all bits are
simply passed through transparently.
I
When operating in UPSR mode VT_V5_INS[1—28] = 1 (
Table 212 on page 171
), only a new BIP-2 and signal
label is generated and inserted while all other bits are programmed from the received LOPOH serial access
channel storage. BIP-2 will be automatically calculated and inserted. The signal label is determined based on
bits VT_TX_MAPTYPE[1—28][3:0] (
Table 211
) and automatically inserted.
I
AIS-V is forced by setting bit VT_AIS_INS[1—28] (
Table 211
) to a 1. AIS-V consists of overwriting the entire VT,
including V1~4, with all ones.
I
Bits VT_TX_MAPTYPE[1—28][3:0] may be programmed to insert an UNEQ-V signal label.
See Table 574 on
page 451
.
I
User-controlled bits VT_BIP2ERR_INS[1—28][1:0] (
Table 212
) will force BIP-2 errors for troubleshooting pur-
poses. See
Table 572
for error insertion modes.
Table 572. BIP-2 Error Insertion Modes
I
When operating in UPSR mode VT_V5_INS[1—28] = 1, REI-V is set to the value in the received LOPOH serial
access channel storage when enabled by bit VT_REI_EN[1—28] =1 (
Table 211 on page 170
). When operating
in normal mode VT_V5_INS[1—28] = 0, REI-V is set to 1 for any detected BIP-2 errors in the corresponding
received VT when enabled by bit VT_REI_EN = 1. Otherwise, the REI-V bit is set to 0.
I
RFI-V is supported. Manual control of the RFI-V bit is enabled with bit VT_RFI_EN[1—28] = 1 (
Table 211
). The
RFI-V bit is programmed with the value of bit VT_RFI_INS[1—28] (
Table 213 on page 171
). When
VT_RFI_EN[1—28] = 0 and operating in UPSR mode VT_V5_INS[1—28] = 1, RFI-V is set to the value in the
received LOPOH serial access channel storage. Otherwise, RFI-V is automatically generated and inserted as
defined in
Table 573 on page 451
. When operating in byte-synchronous mode, RFI-V is also based on the
incoming DS1 RAI from the framer.
I
One bit RDI-V is supported when bit VT_TX_ERDI_EN[1—28] = 0 (
Table 211
). Manual control of the RDI-V bit is
enabled with bit VT_RDI_EN[1—28] = 1 (
Table 211
). The RDI_V bit is programmed with the value of bit
VT_RDI_INS[1—28] (
Table 213
). When VT_RDI_EN[1—28] = 0 and is operating in UPSR mode
VT_V5_INS[1—28] = 1 (
Table 212
), RDI-V is set to the value in the received LOPOH serial access channel stor-
age. Otherwise, RDI-V is automatically generated and inserted as defined in
Table 573
.
Bit 1
Bit 2
Bit 3
REI-V
Bit 4
RFI-V
Bit 5
Bit 6
Bit 7
Bit 8
RDI-V
BIP-2
SIGNAL LABEL
VT_BIP2ERR_INS[1—28][1:0]
(
See Table 212 on page 171
.)
00
01
10
Action
No BIP-2 errors inserted.
Insert continuous BIP-2 errors.
Insert BIP-2 errors based on microprocessor register bit
SMPR_BER_INSRT (
Table 75 on page 68
).
No BIP-2 errors inserted.
11