Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
485
Agere Systems Inc.
21 28-Channel Framer Block Functional Description
(continued)
Table of Contents
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Figures
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Page
Figure 76. Parallel Bus System Interface Mode of the Transmit System Interface ...............................................539
Figure 77. Parallel Bus System Interface Turnaround Timing...............................................................................543
Figure 78. Signals (6-Pin Mode)............................................................................................................................544
Figure 79. Signals (8-Pin Mode)............................................................................................................................544
Figure 80. Network Serial Multiplexed Interface (Single Octet).............................................................................545
Figure 81. Network Serial Multiplexed Interface (Multiple Octets).........................................................................546
Tables
Page
Table 588. Frame Alignment Criteria.....................................................................................................................496
Table 589. Receive Signaling Link Registers 0—31 Bit Description......................................................................498
Table 590. Receive Signaling Link Registers 0—31 G-Bit and F-Bit Description..................................................498
Table 591. Receive Signaling Link Registers 0—31 DS1/CEPT/CMI Data...........................................................500
Table 592. Receive Signaling Link Registers 0—31 Expected Data .....................................................................501
Table 593. Signaling Receive Global Register 3, Bit Definition .............................................................................502
Table 594. Transmit Signaling Link Registers 0—31 Bit Description.....................................................................505
Table 595. Transmit Signaling Link Registers 0—31 G-Bit and F-Bit Description.................................................505
Table 596. Transmit Signaling Link Registers 0—31 DS1/CEPT/CMI Data ..........................................................506
Table 597. Transmit Signaling Link Registers 0—31 Expected Data ....................................................................507
Table 598. Performance Monitor Functional Descriptions.....................................................................................510
Table 599. Performance Report Message Format.................................................................................................514
Table 600. Performance Report Message Field Definition ....................................................................................514
Table 601. Shared Rx Stack Format for SLC-96 Frames......................................................................................516
Table 602. Shared Rx FDL Stack Format for DDS Frames...................................................................................517
Table 603. Shared Rx Stack Format for CEPT Frames.........................................................................................517
Table 604. Shared Tx FDL Stack Format for SLC-96 Frames...............................................................................520
Table 605. Shared Tx FDL Stack Format for DDS Frames ...................................................................................521
Table 606. Shared Tx Stack Format for CEPT Frame...........................................................................................522
Table 607. HDLC Frame Format ...........................................................................................................................524
Table 608. Performance Report Message Structure .............................................................................................528
Table 609. Clock Mode Programming for PLL Mode Device Pins.........................................................................529
Table 610. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames........................................536
Table 611. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels.................................537
Table 612. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT...................................................537
Table 613. Programming Values for FRM_TOFF[2:0] and FRM_ROFF[2:0] when FRM_CMS = 0 ......................537
Table 614. Programming Values for FRM_TOFF[2:0] when FRM_CMS = 1.........................................................537
Table 615. Programming Values for FRM_ROFF[2:0] when FRM_CMS = 1 ........................................................537
Table 616. Parallel System Bus Interface Time-Slot Arrangement for DS1...........................................................541
Table 617. Parallel System Bus Interface Time-Slot Arrangement for E1.............................................................542
Table 618. PSB System I/O Definition...................................................................................................................542
Table 619. Serial ID ...............................................................................................................................................545
Table 620. Current Number of Global and Per-Link/Channel Registers for Each Block........................................547
Table 621. Framer Addressing Map for the Global and Per-Link/Channel Registers of the Superframer.............548