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參數(shù)資料
| 型號： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數(shù)： | 13/61頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
[ Table 3 ] Boundary Scan Exit Order
NOTE :
1. When the device is in scan mode, the mirror function will be disabled and none of the pins are remapped.
2. Since the other input of the MUX for DM0 tied to GND, the device will output the continuous zeros after scanning a bit #67, if the chip stays in scan shift mode.
3. Two RFU balls(#57and #58) in the scan order, will be read as a logic"0".
[ Table 4 ] Scan Pin Description
NOTE :
1. When SEN is asserted, no commands are to be executed by the GDDR3. This applies to both user commands and manufacturing commands which may exist while RES is
deasserted.
2. All scan functionalities are valid only after the appropriate power-up and initialization sequence. (RES and CKE, to set the ODT of the C/A)
3. In scan mode, the ODT for the address and control lines set to a nominal termination value of ZQ. The ODT for DQ’s will be disabled. It is not necessary for the termination
to be calibrated.
4. In a double-load clam-shell configuration, SEN will be asserted to both devices. Separate two SOE’s should be provided to top and bottom devices to access the scanned
output. When either of the devices is in scan mode, SOE for the other device which not in a scan will be disabled.
BIT#
BALL
BIT#
BALL
BIT#
BALL
BIT#
BALL
BIT#
BALL
BIT#
BALL
1
D-3
13
E-10
25
K-11
37
R-10
49
L-3
61
G-4
2
C-2
14
F-10
26
K-10
38
T-11
50
M-2
62
F-4
3
C-3
15
E-11
27
K-9
39
T-10
51
M-4
63
F-2
4
B-2
16
G-10
28
M-9
40
T-3
52
K-4
64
G-3
5
B-3
17
F-11
29
M-11
41
T-2
53
K-3
65
E-2
6
A-4
18
G-9
30
L-10
42
R-3
54
K-2
66
F-3
7
B-10
19
H-9
31
N-11
43
R-2
55
L-4
67
E-3
8
B-11
20
H-10
32
M-10
44
P-3
56
J-3
9
C-10
21
H-11
33
N-10
45
P-2
57
J-2
10
C-11
22
J-11
34
P-11
46
N-3
58
H-2
11
D-10
23
J-10
35
P-10
47
M-3
59
H-3
12
D-11
24
L-9
36
R-11
48
N-2
60
H-4
Package Ball
Symbol
Normal
Function
Type
Description
V-9
SSH
RES
Input
Scan shift.
Capture the data input from the pad at logic LOW and shift the data on the chain at
logic HIGH.
F-9
SCK
CS
Input
Scan Clock. Not a true clock, could be a single pulse or series of pulses.
All scan inputs will be referenced to rising edge of the scan clock.
D-2
SOUT
WDQS0
Output
Scan Output.
V-4
SEN
RFU
Input
Scan Enable.
Logic HIGH would enable the device into scan mode and will be disabled at logic
LOW. Must be tied to GND when not in use.
A-9
SOE
MF
Input
Scan Output Enable.
Enables (registered LOW) and disables (registered HIGH) SOUT data.
This pin will be tied to VDD or GND through a resistor (typically 1K
Ω ) for normal
operation. Tester needs to overdrive this pin guarantee the required input logic level in
scan mode.
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