參數(shù)資料
型號(hào)： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù)： 47/61頁
文件大?。?/td> 1364K
代理商： K4J52324KI-HC1A0
- 51 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
9.3 Clock Input Operating Conditions
Recommended operating conditions (0
°C ≤ Tc ≤85°C)
NOTE : 1. For AC operations, all DC clock requirements must be satisfied as well.
2. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
3. VID is the magnitude of the difference between the input level in CK and the input level on CK.
4. The CK and CK input reference level (for timing referenced to CK and /CK) is the point at which CK and CK cross;
the input reference level for signals other than CK and CK is VREF.
5. CK and CK input slew rate must be > 3V/ns
NOTE : 1. Outputs measured into equivalent load of 10pf at a driver impedance of 40
Ω.
Figure 24. Output Load Circuit
9.4 Capacitance (VDD=1.8V, TA= 25°C, f=1MHz)
9.5 Thermal Characteristics ( 2.6Gbps at VDD=1.8V + 0.1V, VDDQ=1.8V + 0.1V )
NOTE : 1.Measurement procedures for each parameter must follow standard procedures defined in the current JEDEC JESD-51 standard.
2. Theta_JA and Theta_JB must be measured with the high effective thermal conductivity test board defined in JESD51-7
3. Airflow information must be documented for Theta JA.
4. Max_Tj and Max_Tc are documented for normal operation in this table. These are not intended to reflect reliablility limits.
5. Theta_JA should only be used for comparing the thermal performance of single packages and not for system related junction.
6. Theta_JB and Theta_JC are derived through a package thermal simulation and measurement.
Parameter/ Condition
Symbol
Min
Max
Unit
NOTE
Clock Input Mid-Point Voltage; CK and CK
VMP(DC)
VDDQ*0.7-0.1V
VDDQ*0.7+0.1V
V
1,2
Clock Input Voltage Level; CK and CK
VIN(DC)
0.42
VDDQ + 0.3
V
1
Clock Input Differential Voltage; CK and CK
VID(DC)
0.22
VDDQ + 0.5
V
1,3
Clock Input Differential Voltage; CK and CK
VID(AC)
0.22
VDDQ + 0.3
V
3
Clock Input Crossing Point Voltage; CK and CK
VIX(AC)
VREF - 0.15
VREF + 0.15
V
2
Parameter
Symbol
Min
Max
Unit
Input capacitance ( CK, CK )
CIN1
1.5
3.0
pF
Input capacitance (A0~A11, BA0~BA2)
CIN2
1.5
3.0
pF
Input capacitance( CKE, CS, RAS,CAS, WE )
CIN3
1.5
3.0
pF
Data & DQS input/output capacitance(DQ0~DQ31)
COUT
1.5
2.0
pF
Input capacitance(DM0 ~ DM3)
CIN4
1.5
2.0
pF
Parameter
Description
Value
Units
NOTE
Theta_JA
Thermal resistance junction to ambient
38.8
°C/W
Thermal measurement : 1,2,3,5
Max_Tj
Maximum operating junction temperature
73.1
°C
2.6Gbps@2.1V : 4
Max_Tc
Maximum operating case temperature
65.0
°C
2.6Gbps@2.1V : 4
Theta_Jc
Thermal resistance junction to case
6.6
°C/W
Thermal measurement : 1, 6
Theta_JB
Thermal resistance junction to board
14.5
°C/W
Thermal simulation : 1, 2, 6
ZQ
GDDR3
VREF
240 Ω
0.7*VDDQ
Z0=60 Ω
60Ω
VDDQ
10pf
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