參數(shù)資料
型號(hào): K4J52324KI-HC1A0
元件分類: DRAM
英文描述: 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁(yè)數(shù): 28/61頁(yè)
文件大小: 1364K
代理商: K4J52324KI-HC1A0
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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
NOTE : 1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g).
2. Burst length = 4
3. n’ or x or b’ or g’ indicates the next data-out following DO n or DO x or DO b OR DO g, respectively
4. READs are to an active row in any bank.
5. Shown with nominal tAC and tDQSQ.
6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
Figure 14. Random READ Accesses
DON’T CARE
TRANSITIONING DATA
NOP
READ
NOP
READ
T0
T1
T2
T8
T8n
T9
T10
CK
COMMAND
ADDRESS
RDQS
DQ
Bank a,
Col n
CL = 8
DO
n
Bank a,
Col b
T10n
T9n
DO
b
DO
n
DO
n
DO
n
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