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K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
[ Table 11 ] CURRENT STATE BANK n - COMMAND TO BANK n
NOTE :
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see CKE Truth Table) and after tXSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
3. Current state definitions :
Idle : The bank has been precharged, and tRP has been met.
Row Active : A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read : A READ burst has been initiated, with auto precharge disabled.
Write : A WRITE burst has been initiated, with auto precharge disabled.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank
should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and truth table- current state
bank n command to bank n. and according to truth table - current state bank n -command to bank m.
Precharging : Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating : Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the :row active" state.
Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends
Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends
Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during
these states.
Refreshing : Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the GDDR3(x32) will be in the all banks idle state.
Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when tMRD
has been met. Once tMRD is met, the GDDR3(x32) SGRAM will be in the all banks idle state.
Precharge All : Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
10. Requires appropriate DM masking.
11. A WRITE command may be applied after the completion of the READ burst.
CURRENT STATE
CS
RAS
CAS
WE
COMMAND/ ACTION
NOTE
Any
H
X
DESELECT (NOP/ continue previous operation)
L
H
NO OPERATION (NOP/continue previous operation)
X
H
L
H
DATA TERMINATOR DISABLE
Idle
L
H
ACTIVE (Select and activate row)
L
H
AUTO REFRESH
7
Row Active
L
LOAD MODE REGISTER
7
L
H
L
H
READ (Select column and start READ burst)
9
L
H
L
WRITE (Select Column and start WRITE burst)
9
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
Read
(Auto-Precharge
Disable)
L
H
L
H
READ (Select column and start new READ burst)
9
L
H
L
WRITE (Select column and start WRITE burst)
9, 11
L
H
L
PRECHARGE (Only after the READ burst is complete)
8
Write
(Auto-Precharge
Disabled)
L
H
L
H
READ (Select column and start READ burst)
9, 10
L
H
L
WRITE (Select column and start new WRITE burst)
9
L
H
L
PRECHARGE (Only after the WRITE burst is complete)
8, 10