參數(shù)資料
型號(hào)： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁(yè)數(shù)： 39/61頁(yè)
文件大?。?/td> 1364K
代理商： K4J52324KI-HC1A0
- 44 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
7.9.4 Precharge
* Once the device enters the power down mode, it should be in NOP state at least for 10ns. The minimum duration for the power
down mode once CKE brought to down should be at least 10ns.
Figure 23. Power-Down
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row
in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP)
after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1, BA2 select
the bank. When all banks are to be precharged, inputs BA0, BA1, BA2 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to the bank.
7.9.5 Power-Down (CKE Not Active)
Unlike SDR SGRAMs,GDDR3(x32) SGRAM requires CKE to be active at all times an access is in
progress; from the issuing of a READ or WRITE command until completion of the burst. For READs,
a burst completion is defined when the Read Postamble is satisfied; For WRITEs, a burst comple-
tion is defined BL/2 cycles after the Write Postamble is satisfied.
Power-down is entered when CKE is registered LOW. If power-down occurs when there is a row
active in any bank, this mode is referred to as active power-down. Entering power-down deactivates
the input and output buffers, excluding CK,/CK and CKE. For maximum power savings, the user has
the option of disabling the DLL prior to entering power-down. However, power-down duration is lim-
ited by the refresh requirements of the device, so in most applications, the self-refresh mode is pre-
ferred over the DLL-disabled power-down mode.
When in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the
GDDR3 SGRAM, while all other input signals are “Don’t Care” except data terminator disable com-
mand.
The power-down state is synchronously exited when CKE is registered HIGH (in conjunction with a
NOP or DESELECT command). A valid executable command may be applied tPDEX later.
ALL BANKS
ONE BANK
BA
CS
RAS
CAS
WE
A0-A7, A9-A11
BA0,1,2
BA=Bank Address
CK
CKE
HIGH
A8
(if A8 is LOW; otherwise "Don’t Care")
PRECHARGE Command
DON’T CARE
NOP
VALID
T0
T1
Ta0
Ta1
Ta2
CK
COMMAND
VALID
Ta7
T2
CKE
tIS
tPDEX
tIS
No PEAD/WRITE
access in progress
* Enter power - down mode
Exit power - down mode
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