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參數(shù)資料
| 型號： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數(shù)： | 31/61頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
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- 37 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
7.9.3 WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure. The starting column and bank
addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for
that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the
burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered in a rising edge of WDQS following
the WRITE latency set in the mode register and subsequent data elements will be registered on successive
edges of WDQS. Prior to the first valid WDQS edge a half cycle is needed and specified as the WRITE Pre-
amble; the half cycle in WDQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first valid falling edge of WDQS (tDQSS) is specified with a
relative to the write latency. All of the WRITE diagrams show the nominal case, and where the two extreme
cases (i.e., tDQSS(min) and tDQSS(max)) might not be intuitive, they have also been included. Write Burst fig-
ure shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst,
assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data
will be ignored. Data for any WRITE burst may not be truncated with a subsequent WRITE command. The
new WRITE command can be issued on any positive edge of clock following the previous WRITE command
after the burst has completed. The new WRITE command should be issued x cycles after the first WRITE
command should be equals the number of desired nibbles (nibbles are required by 4n-prefetch architec-
ture).
An example of nonconsecutive WRITEs is shown in Nonconsecutive WRITE to READ figure. Full-speed
random write accesses within a page or pages can be performed as shown in Random WRITE cycles fig-
ure. Data for any WRITE burst may be followed by a subsequent READ command.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE
the WRITE burst, tWR should be met as shown in WRITE to PRECHARGE figure.
Data for any WRITE burst can not be truncated by a subsequent PRECHARGE command.
CK
CA
EN AP
DIS AP
BA
CS
RAS
CAS
WE
A0-A7, A9
A10, A11
A8
BA0,1,2
CKE
HIGH
WRITE Command
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
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