參數(shù)資料
型號(hào): K4J52324KI-HC1A0
元件分類(lèi): DRAM
英文描述: 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝: HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁(yè)數(shù): 6/61頁(yè)
文件大?。?/td> 1364K
代理商: K4J52324KI-HC1A0
- 14 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
TEST MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8-A11 set to the
desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0-A6 and A8-A11 set to the desired
values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden from the user.
DLL RESET
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A7 set to zero, and bits A0-A6 and A8-A11 set to the
desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0-A7 and A9-A11 set to the
desired values. When a DLL Reset is complete the GDDR3 SGRAM reset bit 8 of the mode register to a zero.
After DLL Reset MRS, Power down can not be issued within 10 clock.
In case the clock frequency need to be changed after the power-up, 512Mb GDDR3 doesn’t require DLL reset. Instead, DLL should be disabled first
before the frequency changed and then change the clock frequency as needed. After the clock frequency changed, there needed some time till clock
become stable and then enable the DLL and then 20K cycle required to lock the DLL.
Figure 1. Clock frequency change sequence after the power-up(example)
Command
Wait until
CK
700Mbps
1000Mbps
EMRS
DLL Disable
clock stable
EMRS
DLL Enable
20K cycle for
DLL locking time
~~
Any
Command
CK
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