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參數(shù)資料
| 型號： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數(shù)： | 7/61頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
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- 15 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
7.4 Extended Mode Register Set (EMRS)
The extended mode register stores the data output driver strength and on-die termination options. The extended mode register is written by asserting low
on CS, RAS, CAS, WE and high on BA0(The GDDR3 SGRAM should be in all bank precharge with CKE already high prior to writing into the extended
mode register). The state of address pins A0 ~ A11 and BA0,BA1,BA2 in the same cycle as CS, RAS, CAS and WE going low are written in the extended
mode register. The minimum clock cycles specified as tMRD are required to complete the write operation in the extended mode register. 4 kinds of the
output driver strength are supported by EMRS (A1, A0) code. The mode register contents can be changed using the same command and clock cycle
requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific codes.
BA2
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DLL
A6
DLL
0
Enable
1
Disable
RFU
0
1
Term
ID
RON
0
tWR
DLL
tWR
Termination
Driver Strength
BA1
BA0
An ~ A0
00
MRS
01
EMRS
ADDR/CMD Termination
A11
Termination
0
Default
1
Half of default
Vendor ID
A10
Vendor ID
0Off
1On
tWR
A7
A5
A4
tWR
000
11
001
13
010
5
011
6
100
7
101
8
110
9
111
10
Drive Strength
A1
A0
Driver Strength
00
Autocal
01
30
Ω
10
40
Ω
11
50
Ω
Data Termination
A3
A2
Termination
00
ODT Disabled*1
01
Reserved
10
ZQ/4
11
ZQ/2
* ZQ : Resistor connection pin for On-die termination
RFU(Reserved for future use) should stay "0" during EMRS cycle
* 1 : ALL ODT will be disabled
Default value is determined by
CKE status at the rising edge of
RESET during power-up
Ron of Pull-up
A9
RON
040
Ω
160
Ω
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