- 您現在的位置：買賣IC網 > PDF目錄296260 > K4J52324KI-HC1A0 512M X 1 DDR DRAM, 0.2 ns, PBGA136 PDF資料下載
參數資料
| 型號： | K4J52324KI-HC1A0 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 1 DDR DRAM, 0.2 ns, PBGA136 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-136 |
| 文件頁數： | 61/61頁 |
| 文件大?。?/td> | 1364K |
| 代理商： | K4J52324KI-HC1A0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當前第61頁
- 9 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
7.2 Initialization
GDDR3 SGRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those speci-
fied may result in undefined operation.
1. Apply power and keep CKE/RESET at low state (All other inputs may be undefined)
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. (Inputs are not recognized as valid until after VREF is applied)
- The VDD voltage ramp time must be no greater than 200ms from 300mV to VDDmin and the VDD voltage ramps are without any
slope reversal
2. Required minimum 100us for the stable power before RESET pin transition to HIGH
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
be in a High-Z state, all active terminators off, and all DLLs off.
3. Minimum 200us delay required prior to applying any executable command after stable power and clock. During this time, CKE
should be brought to high and DESELECT or NOP command should be applied.
4. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied.
5. Issue a PRECHARGE ALL command following after NOP command.
6. Issue a EMRS command (BA1BA0="01") to enable the DLL.
7. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
20K clock cycles are required to lock the DLL.
8. Issue a PRECHARGE ALL command
9. Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
Following these requirements, the GDDR3 SGRAM is ready for normal operation.
CODE
VDD
VDDQ
VREF
CK
RES
CKE
COMMAND
DM
A0-A7, A9-A11
A8
BA0, BA1
RDQS
WDQS
DQ
RA
CODE
RA
CODE
BAO=H,
BA
NOP
PRE
LMR
PRE
AR
ACT
High
BA1 =L
BAO=L,
BA1 =L
tRP
tMRD
tRFC
tRP
tRFC
Load Extended
Mode Register
tMRD
20K
Load Mode
Register
tIS
tIH
CODE
tIS
tIH
tIS
tIH
tIS
tIH
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
tCH
tCL
tIS
tIH
Precharge
All Banks
Precharge
All Banks
1st
Auto Refresh
2nd
Auto Refresh
DLL Reset
ALL BANKS
T=10ns
Power-up:
VDD and Clock stable
T = 200us
tATS
tATH
T = 100us
相關PDF資料 |
PDF描述 |
|---|---|
| K4M64163PK-BE900 | 4M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| K507 | 2 ELEMENT, 2000 uH, GENERAL PURPOSE INDUCTOR |
| K001 | 2 ELEMENT, 2000 uH, GENERAL PURPOSE INDUCTOR |
| K004 | 2 ELEMENT, 500 uH, GENERAL PURPOSE INDUCTOR |
| K5A22NAU | KEYPAD SWITCH, SPST, MOMENTARY, 0.1A, 50VDC, 2 N, SURFACE MOUNT-STRAIGHT |
相關代理商/技術參數 |
參數描述 |
|---|---|
| K4J52324QC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-AC20000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC - Trays |
| K4J52324QC-BC14 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
| K4J52324QC-BC14000 | 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays |
| K4J52324QC-BC16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。